--- /dev/null
+G04 start of page 2 for group 0 idx 0\r
+G04 Title: (unknown), solder *\r
+G04 Creator: pcb 20070208 *\r
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *\r
+G04 For: santini *\r
+G04 Format: Gerber/RS-274X *\r
+G04 PCB-Dimensions: 710000 410000 *\r
+G04 PCB-Coordinate-Origin: lower left *\r
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--- /dev/null
+G04 start of page 5 for group -4062 idx -4062\r
+G04 Title: (unknown), soldermask *\r
+G04 Creator: pcb 20070208 *\r
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *\r
+G04 For: santini *\r
+G04 Format: Gerber/RS-274X *\r
+G04 PCB-Dimensions: 710000 410000 *\r
+G04 PCB-Coordinate-Origin: lower left *\r
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--- /dev/null
+G04 start of page 8 for group -3984 idx -3984\r
+G04 Title: (unknown), fab *\r
+G04 Creator: pcb 20070208 *\r
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *\r
+G04 For: santini *\r
+G04 Format: Gerber/RS-274X *\r
+G04 PCB-Dimensions: 710000 410000 *\r
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--- /dev/null
+G04 start of page 3 for group 1 idx 3\r
+G04 Title: (unknown), component *\r
+G04 Creator: pcb 20070208 *\r
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *\r
+G04 For: santini *\r
+G04 Format: Gerber/RS-274X *\r
+G04 PCB-Dimensions: 710000 410000 *\r
+G04 PCB-Coordinate-Origin: lower left *\r
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--- /dev/null
+G04 start of page 4 for group -4063 idx -4063\r
+G04 Title: (unknown), componentmask *\r
+G04 Creator: pcb 20070208 *\r
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *\r
+G04 For: santini *\r
+G04 Format: Gerber/RS-274X *\r
+G04 PCB-Dimensions: 710000 410000 *\r
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--- /dev/null
+G04 start of page 7 for group -4079 idx -4079\r
+G04 Title: (unknown), topsilk *\r
+G04 Creator: pcb 20070208 *\r
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *\r
+G04 For: santini *\r
+G04 Format: Gerber/RS-274X *\r
+G04 PCB-Dimensions: 710000 410000 *\r
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# release: pcb 20070208
-# date: Tue Aug 26 15:58:42 2008
+# date: Tue Aug 26 17:05:17 2008
# user: santini (Diego Caberlon Santini,,,)
# host: eniac.eniac
Via[322500 20000 4000 2000 0 2000 "" ""]
Via[622500 287500 6000 2000 0 3500 "" ""]
Via[400000 322500 6000 2000 0 3500 "" ""]
-Via[220000 145000 6000 2000 0 3500 "" ""]
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Via[387500 332500 6000 2000 0 3500 "" ""]
Via[360000 15000 6000 2000 0 3500 "" ""]
Via[175000 90000 6000 2000 0 3500 "" ""]
Line[542500 117500 547500 122500 1000 2000 ""]
Line[510000 15000 505000 20000 2500 2000 ""]
Line[470000 172500 477500 180000 2500 2000 "clearline"]
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Line[477500 352500 477500 360000 2500 2000 "clearline"]
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Line[267500 82500 267500 57500 2500 2000 ""]
Line[235000 22500 235000 27500 2500 2000 "clearline"]
Line[332500 62500 332500 70000 2500 2000 ""]
Line[175000 22500 177500 20000 2500 2000 "clearline"]
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Line[200000 87500 200000 85000 2500 2000 "clearline"]
Line[200000 85000 202500 82500 2500 2000 "clearline"]
Line[202500 82500 215000 82500 2500 2000 "clearline"]
Line[70300 97500 70000 97200 1000 2000 "clearline"]
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Line[155000 57500 155000 52500 2500 2000 "clearline"]
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- Line[202500 50000 205000 52500 2500 2000 "clearline"]
- Line[205000 52500 205000 57500 2500 2000 "clearline"]
Text[75000 390000 0 100 "AIC-2.1.0 (c) 2008" "auto"]
Text[75000 382500 0 100 "Diego Caberlon Santini" "auto"]
Text[75000 375000 0 100 "Walter Fetter Lages" "auto"]
Line[240000 120000 240000 87500 2500 2000 "clearline"]
Line[237500 122500 240000 120000 2500 2000 "clearline"]
Line[80000 80900 80900 80000 1000 2000 ""]
- Line[547500 380000 322500 380000 4000 2000 "clearline"]
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Line[500000 92500 482500 92500 1000 2000 ""]
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Line[547500 35000 547500 62500 1000 2000 ""]
Line[297500 27500 290000 35000 2500 2000 ""]
Line[290000 35000 290000 70000 2500 2000 ""]
Line[297500 75000 297500 57500 1000 2000 ""]
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Line[547500 360000 547500 330000 2500 2000 "clearline"]
Line[602500 52500 602500 57500 2500 2000 ""]
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Line[415000 22500 415000 82500 1000 2000 "clearline"]
Line[602500 340000 625000 317500 2500 2000 "clearline"]
Line[512500 37500 512500 27500 2500 2000 ""]
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Line[625000 97500 632500 97500 1000 2000 ""]
Line[435000 90000 442500 97500 1000 2000 "clearline"]
Line[622500 100000 625000 97500 1000 2000 ""]
Line[632500 47500 607500 47500 2500 2000 ""]
Line[607500 47500 602500 52500 2500 2000 ""]
Line[430000 130000 430000 135000 1000 2000 ""]
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Line[572500 205000 582500 205000 4000 2000 "clearline"]
Line[372500 132500 372500 370000 4000 2000 "clearline"]
Line[572500 282500 582500 282500 4000 2000 "clearline"]
Line[307500 145000 312500 140000 1000 2000 "clearline"]
Line[312500 140000 312500 87500 1000 2000 "clearline"]
Line[317500 82500 312500 87500 1000 2000 "clearline"]
- Line[200000 87500 200000 90000 2500 2000 "clearline"]
+ Line[85000 97500 85000 100000 1000 2000 "clearline"]
Line[207500 147500 207500 217500 1000 2000 "clearline"]
Line[350000 155000 350000 140000 1000 2000 "clearline"]
Line[492500 112500 492500 155000 1000 2000 "clearline"]
Line[92500 102500 90000 100000 1000 2000 "clearline"]
Line[90000 100000 90000 90900 1000 2000 "clearline"]
Line[90000 90900 80000 80900 1000 2000 "clearline"]
- Line[80000 91800 80000 92500 1000 2000 "clearline"]
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- Line[85000 97500 85000 100000 1000 2000 "clearline"]
- Line[85000 100000 87500 102500 1000 2000 "clearline"]
- Line[87500 102500 87500 155000 1000 2000 "clearline"]
- Text[75000 370000 0 100 "AIC-2.1.0 (c) 2008" "selected"]
+ Line[547500 380000 462500 380000 4000 2000 "clearline"]
+ Line[462500 380000 457500 375000 4000 2000 "clearline"]
+ Line[457500 375000 457500 190000 4000 2000 "clearline"]
+ Line[547500 360000 547500 380000 4000 2000 "clearline"]
+ Text[75000 370000 0 100 "AIC-2.1.0 (c) 2008" ""]
Text[75000 377500 0 100 "Diego Caberlon Santini" ""]
Text[75000 385000 0 100 "Walter Fetter Lages" ""]
)
Connect("C8-2")
Connect("C9-2")
Connect("C10-1")
- Connect("C16-1")
- Connect("C17-2")
Connect("J2-A6")
Connect("J2-A28")
Connect("J2-B28")
Connect("U7-13")
Connect("U7-20")
Connect("U7-28")
- Connect("U8-1")
- Connect("U8-8")
)
Net("+12V" "(unknown)")
(
Connect("C1-1")
Connect("C2-2")
+ Connect("C16-1")
+ Connect("C17-2")
Connect("C19-1")
Connect("C20-2")
Connect("C23-1")
Connect("J2-B29")
Connect("J2-C29")
Connect("U1-1")
+ Connect("U8-1")
+ Connect("U8-8")
Connect("U9-1")
Connect("U9-7")
Connect("U9-14")
--- /dev/null
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value=10uFx16V
}
C 2000 86000 1 0 0 gnd-1.sym
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C 2500 86000 1 0 0 gnd-1.sym
C 2800 86300 1 90 0 capacitor-1.sym
{
N 16400 84600 16400 82000 4
N 2800 82000 16400 82000 4
N 2800 82000 2800 84000 4
+C 9400 80100 1 0 0 12V-plus-1.sym
--- /dev/null
+device
+value
+footprint
\ No newline at end of file
--- /dev/null
+(component-library "./sym")
\ No newline at end of file
--- /dev/null
+v 20041228 1
+B 400 0 3600 5600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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+description=High-Perfomance 16-Bit Digital Signal Controller
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+}
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\ No newline at end of file
--- /dev/null
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projects / aic.git / commitdiff