aic-1.0.0 based on TINI.
--- /dev/null
+# Project specific
+# TINI executable
+*.tini
+
+# Text editor
+# Backup files
+*.~
+*.bak
+
+# C++
+# Prerequisites
+*.d
+
+# Compiled Object files
+*.slo
+*.lo
+*.o
+*.obj
+
+# Precompiled Headers
+*.gch
+*.pch
+
+# Compiled Dynamic libraries
+*.so
+*.dylib
+*.dll
+
+# Fortran module files
+*.mod
+*.smod
+
+# Compiled Static libraries
+*.lai
+*.la
+*.a
+*.lib
+
+# Executables
+*.exe
+*.out
+*.app
+
+# Java
+# Compiled class file
+*.class
+
+# Log file
+*.log
+
+# BlueJ files
+*.ctxt
+
+# Mobile Tools for Java (J2ME)
+.mtj.tmp/
+
+# Package Files #
+*.jar
+*.war
+*.nar
+*.ear
+*.zip
+*.tar.gz
+*.rar
+
+# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
+hs_err_pid*
+
+#TeX
+## Core latex/pdflatex auxiliary files:
+*.aux
+*.lof
+*.log
+*.lot
+*.fls
+*.out
+*.toc
+*.fmt
+*.fot
+*.cb
+*.cb2
+.*.lb
+
+## Intermediate documents:
+*.dvi
+*.xdv
+*-converted-to.*
+
+## Generated if empty string is given at "Please type another file name for output:"
+.pdf
+
+## Bibliography auxiliary files (bibtex/biblatex/biber):
+*.bbl
+*.bcf
+*.blg
+*-blx.aux
+*-blx.bib
+*.run.xml
+
+## Build tool auxiliary files:
+*.fdb_latexmk
+*.synctex
+*.synctex(busy)
+*.synctex.gz
+*.synctex.gz(busy)
+*.pdfsync
+
+## Build tool directories for auxiliary files
+# latexrun
+latex.out/
+
+## Auxiliary and intermediate files from other packages:
+# algorithms
+*.alg
+*.loa
+
+# achemso
+acs-*.bib
+
+# amsthm
+*.thm
+
+# beamer
+*.nav
+*.pre
+*.snm
+*.vrb
+
+# changes
+*.soc
+
+# cprotect
+*.cpt
+
+# elsarticle (documentclass of Elsevier journals)
+*.spl
+
+# endnotes
+*.ent
+
+# fixme
+*.lox
+
+# feynmf/feynmp
+*.mf
+*.mp
+*.t[1-9]
+*.t[1-9][0-9]
+*.tfm
+
+#(r)(e)ledmac/(r)(e)ledpar
+*.end
+*.?end
+*.[1-9]
+*.[1-9][0-9]
+*.[1-9][0-9][0-9]
+*.[1-9]R
+*.[1-9][0-9]R
+*.[1-9][0-9][0-9]R
+*.eledsec[1-9]
+*.eledsec[1-9]R
+*.eledsec[1-9][0-9]
+*.eledsec[1-9][0-9]R
+*.eledsec[1-9][0-9][0-9]
+*.eledsec[1-9][0-9][0-9]R
+
+# glossaries
+*.acn
+*.acr
+*.glg
+*.glo
+*.gls
+*.glsdefs
+
+# gnuplottex
+*-gnuplottex-*
+
+# gregoriotex
+*.gaux
+*.gtex
+
+# htlatex
+*.4ct
+*.4tc
+*.idv
+*.lg
+*.trc
+*.xref
+
+# hyperref
+*.brf
+
+# knitr
+*-concordance.tex
+# TODO Comment the next line if you want to keep your tikz graphics files
+*.tikz
+*-tikzDictionary
+
+# listings
+*.lol
+
+# makeidx
+*.idx
+*.ilg
+*.ind
+*.ist
+
+# minitoc
+*.maf
+*.mlf
+*.mlt
+*.mtc[0-9]*
+*.slf[0-9]*
+*.slt[0-9]*
+*.stc[0-9]*
+
+# minted
+_minted*
+*.pyg
+
+# morewrites
+*.mw
+
+# nomencl
+*.nlg
+*.nlo
+*.nls
+
+# pax
+*.pax
+
+# pdfpcnotes
+*.pdfpc
+
+# sagetex
+*.sagetex.sage
+*.sagetex.py
+*.sagetex.scmd
+
+# scrwfile
+*.wrt
+
+# sympy
+*.sout
+*.sympy
+sympy-plots-for-*.tex/
+
+# pdfcomment
+*.upa
+*.upb
+
+# pythontex
+*.pytxcode
+pythontex-files-*/
+
+# thmtools
+*.loe
+
+# TikZ & PGF
+*.dpth
+*.md5
+*.auxlock
+
+# todonotes
+*.tdo
+
+# easy-todo
+*.lod
+
+# xmpincl
+*.xmpi
+
+# xindy
+*.xdy
+
+# xypic precompiled matrices
+*.xyc
+
+# endfloat
+*.ttt
+*.fff
+
+# Latexian
+TSWLatexianTemp*
+
+## Editors:
+# WinEdt
+*.bak
+*.sav
+
+# Texpad
+.texpadtmp
+
+# Kile
+*.backup
+
+# KBibTeX
+*~[0-9]*
+
+# auto folder when using emacs and auctex
+./auto/*
+*.el
+
+# expex forward references with \gathertags
+*-tags.tex
+
+# standalone packages
+*.sta
+
+# generated if using elsarticle.cls
+*.spl
--- /dev/null
+import br.ufrgs.eletro.AIC.*;
+import com.dalsemi.system.*;
+import java.io.*;
+import java.lang.Math.*;
+
+class BrakeTest
+{
+ static final int BASE=0x800000;
+ static final int ST=1000;
+
+ static AIC aic;
+
+ private static void delay(int ms)
+ {
+ long time=TINIOS.uptimeMillis();
+ while(TINIOS.uptimeMillis() < time+ms);
+ }
+
+ public static void main(String[] args) throws IOException
+ {
+ int i;
+ boolean run=true;
+
+ System.out.println("AIC Brake Test Program");
+ System.out.println("Copyright (C) Walter Fetter Lages, 2002.\n");
+
+ try
+ {
+ aic=new AIC(BASE,24.0,20e3,2000);
+
+ aic.on();
+
+ while(run)
+ {
+ aic.brake.release();
+ System.out.println("Brake released");
+ delay(ST);
+ aic.brake.apply();
+ System.out.println("Brake applied");
+ delay(ST);
+ }
+ aic.off();
+ }
+ catch (IllegalAddressException iae)
+ {
+ iae.printStackTrace();
+ }
+
+ }
+}
--- /dev/null
+CLASSPATH=-classpath /opt/tini/bin/tini.jar:/opt/tini/bin/tiniclasses.jar:../lib/AIC.jar
+APIDBPATH=-d /opt/tini/bin/tini.db
+LIBPATH=-path ../lib/AIC.jar
+JAVAFLAGS=-O -target 1.1
+
+all: BrakeTest.tini
+
+BrakeTest.class: BrakeTest.java
+ javac ${JAVAFLAGS} ${CLASSPATH} BrakeTest.java
+
+BrakeTest.tini: BrakeTest.class
+ java ${CLASSPATH} TINIConvertor -f BrakeTest.class ${APIDBPATH} -o BrakeTest.tini ${LIBPATH}
+
+clean:
+ rm -f *.bak *~ BrakeTest.class
+
+distclean: clean
+ rm -f BrakeTest.tini
+
--- /dev/null
+import br.ufrgs.eletro.AIC.*;
+import com.dalsemi.system.*;
+import java.io.*;
+import java.lang.Math.*;
+
+class EncoderTest
+{
+ static final int BASE=0x800000;
+ static final int ST=1500;
+
+ static AIC aic;
+
+ private static void delay(int ms)
+ {
+ long time=TINIOS.uptimeMillis();
+ while(TINIOS.uptimeMillis() < time+ms);
+ }
+
+ static void iter(int i) throws IllegalAddressException
+ {
+ aic.motor.set(10);
+ System.out.print("Motor Voltage: " + i);
+
+ int count=aic.encoder.read();
+ aic.encoder.clear();
+ System.out.print("\tEncocer count: " + count);
+ System.out.println("\tMotor speed: " + (2*java.lang.Math.PI*count/aic.encoder.PULSES/ST*1000));
+ delay(ST);
+ }
+
+ public static void main(String[] args) throws IOException
+ {
+ int i;
+ boolean run=true;
+
+ System.out.println("AIC Encoder Test Program");
+ System.out.println("Copyright (C) Walter Fetter Lages, 2002.\n");
+
+ try
+ {
+ aic=new AIC(BASE,24.0,20e3,2000);
+
+ aic.on();
+
+ aic.brake.release();
+
+ for(i=0;(i <= 24) && run;i++) iter(i);
+
+ while(run)
+ {
+
+ for(i=-24;(i <= 24) && run;i++) iter(i);
+ for(i=24;(i >= -24) && run;i--) iter(i);
+ }
+
+ aic.off();
+
+ }
+ catch (IllegalAddressException iae)
+ {
+ iae.printStackTrace();
+ }
+
+ }
+}
--- /dev/null
+CLASSPATH=-classpath /opt/tini/bin/tini.jar:/opt/tini/bin/tiniclasses.jar:../lib/AIC.jar
+APIDBPATH=-d /opt/tini/bin/tini.db
+LIBPATH=-path ../lib/AIC.jar
+JAVAFLAGS=-O -target 1.1
+
+all: EncoderTest.tini
+
+EncoderTest.class: EncoderTest.java
+ javac ${JAVAFLAGS} ${CLASSPATH} EncoderTest.java
+
+EncoderTest.tini: EncoderTest.class
+ java ${CLASSPATH} TINIConvertor -f EncoderTest.class ${APIDBPATH} -o EncoderTest.tini ${LIBPATH}
+
+clean:
+ rm -f *.bak *~ EncoderTest.class
+
+distclean: clean
+ rm -f EncoderTest.tini
+
--- /dev/null
+Instalar o software da AIC:
+
+<http://www.ece.ufrgs.br/~fetter/pub/aic-x.y.z.tgz>: descompactar no
+diretorio do usuario:
--- /dev/null
+import br.ufrgs.eletro.AIC.*;
+import com.dalsemi.system.*;
+import java.io.*;
+import java.lang.Math.*;
+
+class IndexTest
+{
+ static final int BASE=0x800000;
+ static final int ST=500;
+
+ static AIC aic;
+
+ private static void delay(int ms)
+ {
+ long time=TINIOS.uptimeMillis();
+ while(TINIOS.uptimeMillis() < time+ms);
+ }
+
+ public static void main(String[] args) throws IOException
+ {
+ int i;
+ boolean run=true;
+
+ System.out.println("AIC Index Test Program");
+ System.out.println("Copyright (C) Walter Fetter Lages, 2002.\n");
+
+ try
+ {
+ aic=new AIC(BASE,24.0,20e3,2000);
+
+ aic.on();
+
+ while(run)
+ {
+ System.out.println("Index=" + aic.index.read());
+ delay(ST);
+ }
+ aic.off();
+ }
+ catch (IllegalAddressException iae)
+ {
+ iae.printStackTrace();
+ }
+
+ }
+}
--- /dev/null
+CLASSPATH=-classpath /opt/tini/bin/tini.jar:/opt/tini/bin/tiniclasses.jar:../lib/AIC.jar
+APIDBPATH=-d /opt/tini/bin/tini.db
+LIBPATH=-path ../lib/AIC.jar
+JAVAFLAGS=-O -target 1.1
+
+all: IndexTest.tini
+
+IndexTest.class: IndexTest.java
+ javac ${JAVAFLAGS} ${CLASSPATH} IndexTest.java
+
+IndexTest.tini: IndexTest.class
+ java ${CLASSPATH} TINIConvertor -f IndexTest.class ${APIDBPATH} -o IndexTest.tini ${LIBPATH}
+
+clean:
+ rm -f *.bak *~ IndexTest.class
+
+distclean: clean
+ rm -f IndexTest.tini
+
--- /dev/null
+import br.ufrgs.eletro.AIC.*;
+import com.dalsemi.system.*;
+import java.io.*;
+import java.lang.Math.*;
+
+class JointTest
+{
+ static final int BASE=0x800000;
+
+ static AIC aic;
+
+ private static void delay(int ms)
+ {
+ long time=TINIOS.uptimeMillis();
+ while(TINIOS.uptimeMillis() < time+ms);
+ }
+
+ static void iter(double v,int ms) throws IllegalAddressException
+ {
+ aic.motor.set(v);
+ System.out.print("Motor Voltage: " + v);
+ System.out.println("\tIndex: " + aic.index.read());
+
+ delay(ms);
+ }
+
+ public static void main(String[] args) throws IOException
+ {
+ int i;
+
+ System.out.println("AIC Joint Test Program");
+ System.out.println("Copyright (C) Walter Fetter Lages, 2002.\n");
+
+ try
+ {
+ aic=new AIC(BASE,24.0,20e3,2000);
+
+ aic.on();
+
+ aic.brake.release();
+
+ while(!aic.index.read())
+ {
+ iter(5,1000);
+ iter(-5,1000);
+ }
+ aic.off();
+ }
+ catch (IllegalAddressException iae)
+ {
+ iae.printStackTrace();
+ }
+
+ }
+}
--- /dev/null
+CLASSPATH=-classpath /opt/tini/bin/tini.jar:/opt/tini/bin/tiniclasses.jar:../lib/AIC.jar
+APIDBPATH=-d /opt/tini/bin/tini.db
+LIBPATH=-path ../lib/AIC.jar
+JAVAFLAGS=-O -target 1.1
+
+all: JointTest.tini
+
+JointTest.class: JointTest.java
+ javac ${JAVAFLAGS} ${CLASSPATH} JointTest.java
+
+JointTest.tini: JointTest.class
+ java ${CLASSPATH} TINIConvertor -f JointTest.class ${APIDBPATH} -o JointTest.tini ${LIBPATH}
+
+clean:
+ rm -f *.bak *~ JointTest.class
+
+distclean: clean
+ rm -f JointTest.tini
+
--- /dev/null
+CLASSPATH=-classpath /opt/tini/bin/tini.jar:/opt/tini/bin/tiniclasses.jar:../lib/AIC.jar
+APIDBPATH=-d /opt/tini/bin/tini.db
+LIBPATH=-path ../lib/AIC.jar
+JAVAFLAGS=-O -target 1.1
+
+all: MotorReset.tini
+
+MotorReset.class: MotorReset.java
+ javac ${JAVAFLAGS} ${CLASSPATH} MotorReset.java
+
+MotorReset.tini: MotorReset.class
+ java ${CLASSPATH} TINIConvertor -f MotorReset.class ${APIDBPATH} -o MotorReset.tini ${LIBPATH}
+
+clean:
+ rm -f *.bak *~ MotorReset.class
+
+distclean: clean
+ rm -f MotorReset.tini
+
--- /dev/null
+import br.ufrgs.eletro.AIC.*;
+import com.dalsemi.system.*;
+import java.io.*;
+import java.lang.Math.*;
+
+class MotorReset
+{
+ static final int BASE=0x800000;
+
+ static AIC aic;
+
+ private static void delay(int ms)
+ {
+ long time=TINIOS.uptimeMillis();
+ while(TINIOS.uptimeMillis() < time+ms);
+ }
+
+ static void iter(double v,int ms) throws IllegalAddressException
+ {
+ aic.motor.set(v);
+ System.out.print("Motor Voltage: " + v);
+ System.out.println("\tIndex: " + aic.index.read());
+
+ delay(ms);
+ }
+
+ public static void main(String[] args) throws IOException
+ {
+
+ System.out.println("AIC Joint Test Program");
+ System.out.println("Copyright (C) Walter Fetter Lages, 2002.\n");
+
+ try
+ {
+ aic=new AIC(BASE,24.0,20e3,2000);
+
+ aic.on();
+
+ aic.brake.release();
+
+ double v=0;
+
+ while(!aic.index.read())
+ {
+ if(v < 24.0) v++;
+ iter(v,1000);
+ }
+ aic.off();
+ }
+ catch (IllegalAddressException iae)
+ {
+ iae.printStackTrace();
+ }
+
+ }
+}
--- /dev/null
+CLASSPATH=-classpath /opt/tini/bin/tini.jar:/opt/tini/bin/tiniclasses.jar:../lib/AIC.jar
+APIDBPATH=-d /opt/tini/bin/tini.db
+LIBPATH=-path ../lib/AIC.jar
+JAVAFLAGS=-O -target 1.1
+
+all: MotorTest.tini
+
+MotorTest.class: MotorTest.java
+ javac ${JAVAFLAGS} ${CLASSPATH} MotorTest.java
+
+MotorTest.tini: MotorTest.class
+ java ${CLASSPATH} TINIConvertor -f MotorTest.class ${APIDBPATH} -o MotorTest.tini ${LIBPATH}
+
+clean:
+ rm -f *.bak *~ MotorTest.class
+
+distclean: clean
+ rm -f MotorTest.tini
+
--- /dev/null
+import br.ufrgs.eletro.AIC.*;
+import com.dalsemi.system.*;
+import java.io.*;
+import java.lang.Math.*;
+
+class MotorTest
+{
+ static final int BASE=0x800000;
+ static final int ST=100;
+
+ static AIC aic;
+
+ private static void delay(int ms)
+ {
+ long time=TINIOS.uptimeMillis();
+ while(TINIOS.uptimeMillis() < time+ms);
+ }
+
+ static void iter(int i) throws IllegalAddressException
+ {
+ aic.motor.set(i);
+ System.out.println("Motor Voltage: " + i);
+
+ delay(ST);
+ }
+
+ public static void main(String[] args) throws IOException
+ {
+ int i;
+ boolean run=true;
+
+ System.out.println("AIC Motor Test Program");
+ System.out.println("Copyright (C) Walter Fetter Lages, 2002.\n");
+
+ try
+ {
+ aic=new AIC(BASE,24.0,20e3,2000);
+
+ aic.on();
+
+ aic.brake.release();
+
+ for(i=0;(i <= 24) && run;i++) iter(i);
+
+ while(run)
+ {
+ for(i=24;(i >= -24) && run;i--) iter(i);
+ for(i=-24;(i <= 24) && run;i++) iter(i);
+ }
+ aic.off();
+ }
+ catch (IllegalAddressException iae)
+ {
+ iae.printStackTrace();
+ }
+
+ }
+}
--- /dev/null
+ Actuator Interface Card
+
+aic-1.*.* based on TINI
--- /dev/null
+CLASSPATH=-classpath /opt/tini/bin/tini.jar:/opt/tini/bin/tiniclasses.jar
+APIDBPATH=-d /opt/tini/bin/tini.db
+JAVAFLAGS=-O -target 1.1
+
+all: StrobeTest.tini
+
+StrobeTest.class: StrobeTest.java
+ javac ${JAVAFLAGS} ${CLASSPATH} StrobeTest.java
+
+StrobeTest.tini: StrobeTest.class
+ java ${CLASSPATH} TINIConvertor -f StrobeTest.class ${APIDBPATH} -o StrobeTest.tini
+
+clean:
+ rm -f *.bak *~ StrobeTest.class
+
+distclean: clean
+ rm -f StrobeTest.tini
+
--- /dev/null
+import com.dalsemi.system.DataPort;
+import com.dalsemi.system.IllegalAddressException;
+
+class StrobeTest
+{
+ static final int BASE = 0x800000;
+ static final int PWM = BASE+0x80000;
+ static final int ENCODER = BASE+0x90000;
+ static final int CONTROL = BASE+0xa0000;
+
+ public static void main(String[] args)
+ {
+ DataPort pwm = new DataPort(PWM);
+ DataPort encoder = new DataPort(ENCODER);
+ DataPort control = new DataPort(CONTROL);
+
+ pwm.setFIFOMode(true);
+ encoder.setFIFOMode(true);
+ control.setFIFOMode(true);
+
+ pwm.setStretchCycles(DataPort.STRETCH10);
+ encoder.setStretchCycles(DataPort.STRETCH10);
+ control.setStretchCycles(DataPort.STRETCH10);
+
+ try
+ {
+ int data=0;
+
+ for(;;)
+ {
+
+ pwm.write(data);
+ encoder.write(data);
+ control.write(data);
+ data=~data;
+
+ pwm.read();
+ encoder.read();
+ control.read();
+
+ }
+ }
+ catch (IllegalAddressException iae)
+ {
+ iae.printStackTrace();
+ }
+ }
+}
--- /dev/null
+SCHEMS=aictini.sch aicpower.sch
+
+all: doc pcb bom
+
+doc: aic.ps aic.pdf
+
+aic.ps: aic.dvi
+ dvips aic
+
+aic.pdf: aic.dvi
+ dvipdf aic
+
+aic.dvi: aic.tex aic.aux aic.bbl
+ latex aic
+ latex aic
+
+aic.aux: aic.tex
+ latex aic
+
+aic.bbl: aic.bib
+ bibtex aic
+
+pcb: aic.net #aic.pcb
+
+aic.net: $(SCHEMS)
+ gnetlist -g PCB -o aic.net $(SCHEMS)
+
+#aic.pcb: $(SCHEMS)
+# gnetlist -g PCBboard -o aic.pcb $(SCHEMS)
+
+bom: aic.bom aic.bpp aic.xrf
+
+aic.bom: $(SCHEMS) attribs
+ gnetlist -g bom -o aic.bom $(SCHEMS)
+
+aic.bpp: aic.bom
+ bompp.sh aic.bom > aic.bpp
+
+aic.xrf: aic.bom
+ bom_xref.sh aic.bom > aic.xrf
+
+clean:
+ rm -f *.aux *.log *~ *.bak *.bbl *.blg *.old
+
+distclean: clean
+ rm -f aic.ps aic.pdf aic.dvi aic.net aic.bom aic.bpp aic.xrf
+
+update: $(SCHEMS)
+ gschupdate $(SCHEMS)
--- /dev/null
+@misc{ftpfs,
+title="{FTP} File System",
+note="http://ftpfs.sourceforge.net",
+key="FTP File System"}
+
+@misc{javasdk,
+title="{Java 2 SDK}, Standard Edition",
+note="http://java.sun.com/j2se/1.4",
+key="Java 2 {SDK}, Standard Edition"}
+
+@misc{javax.comm,
+title="{Java} extension for Communication ({Java} communications {API})",
+note="http://java.sun.com/products/javacomm",
+key="Java extension for Communication ({Java} communications {API})"}
+
+@misc{sdcc,
+title="{SDCC} - a Freeware, retargettable, optimizing {ANSI-C} compiler",
+note="http://sdcc.sourceforge.net",
+key="SDCC"}
+
+@misc{slush,
+title="{Slush}",
+note="docs/Slush.txt in ftp://ftp.dalsemi.com/pub/tini/tini1\underline{~}10.tgz",
+key="Slush"}
+
+@misc{rxtx,
+title="{RXTX}",
+note="http://www.rxtx.org",
+key="{RXTX}"}
+
+@misc{tinisdk,
+title="{TINI} Runtime Environment",
+note="ftp://ftp.dalsemi.com/pub/tini/tini1 \underline{~} 10.tgz",
+key="{TINI} Runtime Environment"}
+
+@book{tinispec,
+title="The {TINI} Specification and Developers Guide",
+author="Don Loomis",
+publisher="Addison-Wesley",
+address="Boston, MA",
+month="Jun",
+year="2001",
+note="http://www.ibutton.org/TINI/tinispec.pdf"}
+
--- /dev/null
+\documentclass[a4paper,12pt,brazil]{article}
+\usepackage{babel}
+\usepackage{epsf}
+\usepackage{float}
+
+\newcommand{\postscript}[2]
+{\setlength{\epsfxsize}{#2\hsize}
+\centerline{\epsfbox{#1}}}
+
+\renewcommand \thesection{\Roman{section}}
+
+\newtheorem{lemma}{Lema}
+\newtheorem{proof}{Prova}
+
+\title{
+{\large Universidade Federal do Rio Grande do Sul\\
+Escola de Engenharia\\
+Departamento de Engenharia El\'etrica}\\
+Actuator Interface Card}
+
+\author{Prof. Walter Fetter Lages}
+
+\begin{document}
+
+\maketitle
+
+
+\bibliographystyle{abbrv}
+
+\section{Introdu\c{c}\~ao}
+
+
+\section{Mapa de Endere\c{c}os}
+
+O espa\c{c}o de endere\c{c}amento da AIC \'e ocupado por dois conjuntos de
+dispositivos: os dispositivos existentes na pr\'opria TINI e os dispositivos
+externos.
+
+\subsection{Dispositivos da TINI}
+
+O mapa de endere\c{c}os da TINI \'e mostrado na tabela \ref{tab:addmap}.
+Note-se que o software da TINI apresenta para o usu\'ario uma mem\'oria
+linear\cite{tinispec}. Os endere\c{c}os habilitados atrav\'es de $\overline{\mbox{PCE0}}$,
+$\overline{\mbox{PCE1}}$, $\overline{\mbox{PCE2}}$ e
+$\overline{\mbox{PCE3}}$ s\~ao acessados no firmware da TINI atrav\'es das
+faixas 800000H-8FFFFFH, 900000H-9FFFFFH, A00000H-AFFFFFH e
+B00000H-BFFFFFH, respectivamente.
+
+\begin{table}[H]
+\caption{Mapa de Endere\c{c}os da TINI RevD}
+\label{tab:addmap}
+\begin{center}
+\begin{tabular}{ccccc}
+\hline \hline
+Endere\c{c}o & STROBE & Nome & Dispositivo & Refer\^encia\\
+\hline
+000000H - 0FFFFFH & $\overline{\mbox{RCE0}}$ & 512Kx8 FLASH & Flash Memory & U2\\
+100000H - 1FFFFFH & $\overline{\mbox{CE1}}$ & 512Kx8 SRAM & SRAM & U4\\
+200000H - 2FFFFFH & $\overline{\mbox{CE2}}$ & 512Kx8 SRAM & SRAM & U5\\
+300000H - 307FFFH & $\overline{\mbox{CE3}}$ & Ethernet Interface & SMC91C94/96 & U3\\
+308000H - 309FFFH & $\overline{\mbox{CE3}}$ \\
+310000H & $\overline{\mbox{CE3}}$ & Real Time Clock & DS1315 & U7\\
+310001H - 3FFFFFH & $\overline{\mbox{CE3}}$ \\
+000000H - 0FFFFFH & $\overline{\mbox{PCE0}}$\\
+100000H - 1FFFFFH & $\overline{\mbox{PCE1}}$ \\
+200000H - 2FFFFFH & $\overline{\mbox{PCE2}}$ \\
+300000H - 3FFFFFH & $\overline{\mbox{PCE3}}$ \\
+\hline
+\end{tabular}
+\end{center}
+\end{table}
+
+\subsection{Dispositivos Externos}
+
+Os dispositivos externos podem ser mapeados, atrav\'es de jumper, em
+qualquer dos espa\c{c}os de endere\c{c}amento selecionados por
+$\overline{\mbox{PCE0}}$-$\overline{\mbox{PCE3}}$. A tabela \ref{tab:extmap}
+mostra o mapeamento de endere\c{c}os dentro da faixa selecionada pelo
+jumper.
+
+\begin{table}[H]
+\caption{Mapa de Endere\c{c}os de Dispositivos Externos}
+\label{tab:extmap}
+\begin{center}
+\begin{tabular}{cccc}
+\hline \hline
+Endere\c{c}o & Nome & Dispositivo & Refer\^encia\\
+\hline
+X80000H - X80003H & PWM & 8254 & U6\\
+X80004H - X8FFFFH & Alias PWM & 8254 & U6\\
+X90000H & Encoder & HCTL-2016 & U7\\
+X90001H - X9FFFFH & Alias Encoder & HCTL-2016 & U7\\
+XA0000H & Controle & 22V10 & U8\\
+XA0001H - XAFFFFH & Alias Controler & 22V10 & U8\\
+\hline
+\end{tabular}
+\end{center}
+\end{table}
+
+\subsection{Registrador de Controle}
+
+Este registrador (endere\c{c}o XA0000H) \'e implementado em um 22V10 e os
+seus bits est\~ao descritos na tabela \ref{tab:ctrlreg}.
+
+\begin{table}[H]
+\caption{Registrador de Controle}
+\label{tab:ctrlreg}
+\begin{center}
+\begin{tabular}{ccl}
+\hline \hline
+Bit & Opera\c{c}\~ao & Descri\c{c}\~ao\\
+\hline
+D0 & R & \'{\i}ndice\\
+\hline
+D1D0 & W\\
+00 & & Desabilita PWM\\
+01 & & Habilita PWM\\
+10 & & Ativa freio\\
+11 & & Libera freio\\
+\hline
+\end{tabular}
+\end{center}
+\end{table}
+
+\section{Actuator Interface Case}
+
+O gabinete de montagem da AIC possui os conectores de interface RS232, CAN e
+Ethernet no painel frontal e o conector de conex\~ao ao atuador no painel
+traseiro. A pinagem deste conector \'e detalhada na tabela
+\ref{tab:backpinout}.
+
+\begin{table}[H]
+\caption{Pinagem do Conector Traseiro}
+\label{tab:backpinout}
+\begin{center}
+\begin{tabular}{cl}
+\hline \hline
+Pino & Sinal\\
+\hline
+1 & GND Encoder\\
+2 & CHA\\
+3 & +5V\\
+4 & CHB\\
+5 & GND \'Indice\\
+6 & \'Indice\\
+7 & +24V \'Indice\\
+8 & GND\\
+9 & +24V\\
+10 & Freio\\
+11 & Motor +\\
+12 & Motor -\\
+\hline
+\end{tabular}
+\end{center}
+\end{table}
+
+\bibliography{aic}
+
+\end{document}
--- /dev/null
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+T 6800 85800 5 10 1 1 0 7
+value=CAN1TX
+T 7700 85700 5 10 0 1 0 0
+net=CAN1TX:1
+}
+C 6300 86300 1 0 0 input-2.sym
+{
+T 6800 86400 5 10 1 1 0 7
+value=CAN0RX
+T 6300 86300 5 10 0 1 0 0
+net=CAN0RX:1
+}
+C 6300 85400 1 0 0 input-2.sym
+{
+T 6800 85500 5 10 1 1 0 7
+value=CAN1RX
+T 6300 85400 5 10 0 1 0 0
+net=CAN1RX:1
+}
+N 12300 74100 12400 74100 4
+N 12400 74100 12400 74300 4
+N 14000 74100 14800 74100 4
+T 23600 72100 9 9 1 0 0 0
+Walter Fetter Lages & Fernando Pessutto
+U 10700 88400 10700 85600 10 0
+U 12100 85400 12100 88400 10 0
+U 10700 85200 10700 79300 10 0
+U 18300 86900 18300 78400 10 0
+U 26500 88400 26500 78400 10 0
--- /dev/null
+device
+value
+footprint
--- /dev/null
+package br.ufrgs.eletro.AIC;
+import com.dalsemi.system.IllegalAddressException;
+
+public class AIC
+{
+
+ public Motor motor;
+ public Encoder encoder;
+ public Brake brake;
+ public Index index;
+
+ public void on() throws IllegalAddressException
+ {
+ motor.on();
+ encoder.clear();
+ }
+
+ public void off() throws IllegalAddressException
+ {
+ motor.set(0);
+ motor.off();
+ encoder.clear();
+ }
+
+ public AIC(int base,double vm,double freq,int np) throws IllegalAddressException
+ {
+ motor=new Motor(base,vm,freq);
+ encoder=new Encoder(base,np);
+ brake=new Brake(base);
+ index=new Index(base);
+ }
+
+ public void finalize() throws IllegalAddressException
+ {
+ off();
+ }
+
+}
--- /dev/null
+package br.ufrgs.eletro.AIC;
+
+import com.dalsemi.system.DataPort;
+import com.dalsemi.system.IllegalAddressException;
+
+public class Brake
+{
+ private static final int LATCH=0xA0000;
+ private static final int PWMDISABLE=0x00;
+ private static final int PWMENABLE=0x01;
+ private static final int BRAKEAPPLY=0x02;
+ private static final int BRAKERELEASE=0x03;
+
+ private DataPort latch;
+
+ public Brake(int base)
+ {
+ latch=new DataPort(base+LATCH);
+ latch.setFIFOMode(true);
+ latch.setStretchCycles(DataPort.STRETCH10);
+ }
+
+ public void apply() throws IllegalAddressException
+ {
+ latch.write(BRAKEAPPLY);
+ }
+
+ public void release() throws IllegalAddressException
+ {
+ latch.write(BRAKERELEASE);
+ }
+}
+
+
--- /dev/null
+package br.ufrgs.eletro.AIC;
+
+import com.dalsemi.system.DataPort;
+import com.dalsemi.system.IllegalAddressException;
+
+public class Encoder
+{
+
+ public final int PULSES;
+
+ private static final int ENCODER=0x90000;
+
+ private DataPort encPort;
+
+ public void clear() throws IllegalAddressException
+ {
+ encPort.write((byte)0);
+ }
+
+ public Encoder(int base,int pulses) throws IllegalAddressException
+ {
+ PULSES=pulses;
+
+ encPort=new DataPort(base+ENCODER);
+ encPort.setFIFOMode(true);
+ encPort.setStretchCycles(DataPort.STRETCH10);
+
+ clear();
+ }
+
+ public void finalize() throws IllegalAddressException
+ {
+ clear();
+ }
+
+ public int read() throws IllegalAddressException
+ {
+ int count;
+ byte[] hilo=new byte[2];
+ boolean FIFOMode;
+
+ FIFOMode=encPort.getFIFOMode();
+ encPort.setFIFOMode(false);
+ encPort.read(hilo,0,2);
+ encPort.setFIFOMode(FIFOMode);
+
+ count=(((int)hilo[0]) << 8) | (int)hilo[1];
+
+ return count;
+ }
+
+}
+
--- /dev/null
+package br.ufrgs.eletro.AIC;
+
+import com.dalsemi.system.DataPort;
+import com.dalsemi.system.IllegalAddressException;
+
+public class Index
+{
+ private static final int LATCH=0xA0000;
+
+ private DataPort latch;
+
+ public Index(int base) throws IllegalAddressException
+ {
+ latch=new DataPort(base+LATCH);
+ latch.setFIFOMode(true);
+ latch.setStretchCycles(DataPort.STRETCH10);
+ }
+
+ public boolean read() throws IllegalAddressException
+ {
+ if((latch.read() & 0x01) == 1) return true; else return false;
+ }
+
+}
--- /dev/null
+CLASSPATH=-classpath /opt/tini/bin/tini.jar:/opt/tini/bin/tiniclasses.jar:.
+APIDBPATH=-d /opt/tini/bin/tini.db
+PKGPATH=br/ufrgs/eletro/AIC
+JAVAFLAGS=-O -target 1.1
+
+all: AIC.jar
+
+${PKGPATH}/PWM.class: PWM.java
+ javac ${JAVAFLAGS} ${CLASSPATH} -d . PWM.java
+
+${PKGPATH}/Motor.class: Motor.java ${PKGPATH}/PWM.class
+ javac ${JAVAFLAGS} ${CLASSPATH} -d . Motor.java
+
+${PKGPATH}/Encoder.class: Encoder.java
+ javac ${JAVAFLAGS} ${CLASSPATH} -d . Encoder.java
+
+${PKGPATH}/Brake.class: Brake.java
+ javac ${JAVAFLAGS} ${CLASSPATH} -d . Brake.java
+
+${PKGPATH}/Index.class: Index.java
+ javac ${JAVAFLAGS} ${CLASSPATH} -d . Index.java
+
+${PKGPATH}/AIC.class: AIC.java
+ javac ${JAVAFLAGS} ${CLASSPATH} -d . AIC.java
+
+AIC.jar: ${PKGPATH}/PWM.class\
+ ${PKGPATH}/Motor.class\
+ ${PKGPATH}/Encoder.class\
+ ${PKGPATH}/Brake.class\
+ ${PKGPATH}/Index.class\
+ ${PKGPATH}/AIC.class
+ jar cf AIC.jar ${PKGPATH}
+
+clean:
+ rm -rf *.bak *~ br
+
+distclean: clean
+ rm -f AIC.jar
+
--- /dev/null
+package br.ufrgs.eletro.AIC;
+
+import com.dalsemi.system.IllegalAddressException;
+
+public class Motor
+{
+
+ private double volt;
+ private PWM pwm;
+
+ public Motor(int baseadd,double voltage,double freq) throws IllegalAddressException
+ {
+ volt=voltage;
+
+ pwm=new PWM(baseadd,freq);
+ pwm.off();
+ }
+
+ public Motor(int baseadd,double voltage) throws IllegalAddressException
+ {
+ volt=voltage;
+
+ pwm=new PWM(baseadd);
+ pwm.off();
+ }
+
+ public void finalize() throws IllegalAddressException
+ {
+ pwm.off();
+ }
+
+ public void on() throws IllegalAddressException
+ {
+ pwm.on();
+ };
+
+ public void off() throws IllegalAddressException
+ {
+ pwm.off();
+ };
+
+ public double set(double voltage) throws IllegalAddressException
+ {
+ double dutycicle=0.5*voltage/volt+0.5;
+ pwm.setDuty(dutycicle);
+ return dutycicle;
+ };
+};
+
--- /dev/null
+package br.ufrgs.eletro.AIC;
+
+import com.dalsemi.system.DataPort;
+import com.dalsemi.system.IllegalAddressException;
+
+public class PWM
+{
+ private static final int PWM=0x80000;
+
+ private static final int LATCH=0xA0000;
+ private static final int PWMDISABLE=0x00;
+ private static final int PWMENABLE=0x01;
+ private static final int BRAKERELEASE=0x02;
+ private static final int BRAKEAPPLY=0x03;
+
+
+ private static final int ONE_SHOT_BIN=0x32; /* programmable one-shot binary */
+ private static final int RATE_BIN=0x34; /* rate generator binary */
+
+ public static final double REF_FREQ=10e6; /* reference frequency = 10 MHz */
+ public static final double SW_FREQ=20e3; /* default switching frequency = 20 KHz */
+ public static final double TURNOFF_DELAY=600e-9;
+ public static final int MIN_COUNT=(int)(2*TURNOFF_DELAY*REF_FREQ);
+ public static final int MAX_COUNT=(int)(REF_FREQ/SW_FREQ);
+
+ private int max_count=MAX_COUNT;
+
+ private DataPort timer0;
+ private DataPort timer1;
+ private DataPort control;
+
+ private DataPort latch;
+
+ public void setFreq(double frequency) throws IllegalAddressException
+ {
+ max_count=(int)(REF_FREQ/frequency) & 0xffff;
+
+ control.write(RATE_BIN);
+ timer0.write((byte) max_count);
+ timer0.write((byte)(max_count >> 8));
+
+ control.write(0x40 | ONE_SHOT_BIN);
+ timer1.write((byte) (max_count/2));
+ timer1.write((byte)((max_count/2) >> 8));
+ }
+
+ public double getFreq()
+ {
+ return REF_FREQ/max_count;
+ }
+
+ private void init(int base,double freq) throws IllegalAddressException
+ {
+ timer0=new DataPort(base+PWM+0);
+ timer0.setFIFOMode(true);
+ timer0.setStretchCycles(DataPort.STRETCH10);
+
+ timer1=new DataPort(base+PWM+1);
+ timer1.setFIFOMode(true);
+ timer1.setStretchCycles(DataPort.STRETCH10);
+
+ control=new DataPort(base+PWM+3);
+ control.setFIFOMode(true);
+ control.setStretchCycles(DataPort.STRETCH10);
+
+ latch=new DataPort(base+LATCH);
+ latch.setFIFOMode(true);
+ latch.setStretchCycles(DataPort.STRETCH10);
+
+
+ control.write(RATE_BIN);
+
+ timer0.write((byte) MAX_COUNT);
+ timer0.write((byte)(MAX_COUNT >> 8));
+
+ control.write(0x40 | ONE_SHOT_BIN);
+ timer1.write((byte)(max_count/2));
+ timer1.write((byte)((max_count/2) >> 8));
+
+ setFreq(freq);
+ }
+
+ public PWM(int base,double freq) throws IllegalAddressException
+ {
+ init(base,freq);
+ }
+
+ public PWM(int base) throws IllegalAddressException
+ {
+ init(base,SW_FREQ);
+ }
+
+ public void finalize() throws IllegalAddressException
+ {
+ timer1.write((byte)(max_count/2));
+ timer1.write((byte)((max_count/2) >> 8));
+ }
+
+
+ public int setDuty(double dutycicle) throws IllegalAddressException
+ {
+ if(dutycicle < 0.0) dutycicle=0.0;
+ if(dutycicle > 1.0) dutycicle=1.0;
+ int count=(int)(max_count*(1.0-dutycicle));
+ if(count < MIN_COUNT) count=MIN_COUNT;
+ if(count > max_count-MIN_COUNT) count=max_count-MIN_COUNT;
+ timer1.write((byte)count);
+ timer1.write((byte)(count >> 8));
+ return count;
+ }
+
+ public void on() throws IllegalAddressException
+ {
+ latch.write((byte)PWMENABLE);
+ }
+
+ public void off() throws IllegalAddressException
+ {
+ latch.write((byte)PWMDISABLE);
+ }
+}
--- /dev/null
+Groupings\r
+0:0:8;\r
+1:0:10;\r
+2:0:12;\r
+3:0:14;\r
+4:0:16;\r
+5:0:16;\r
+6:0:14;\r
+7:0:12;\r
+8:0:10;\r
+9:0:8;\r
+10:0:1;\r
+11:0:1;\r
+12:0:1;\r
+13:0:1;\r
+14:0:1;\r
+15:0:1;\r
+16:0:1;\r
+17:0:1;\r
+18:0:1;\r
+19:0:1;\r
+20:0:1;\r
+21:0:1;\r
+Declarations\r
+CLK,dir:input;\r
+A19,dir:input;\r
+A18,dir:input;\r
+A17,dir:input;\r
+A16,dir:input;\r
+!WR,dir:input;\r
+!RD,dir:input;\r
+D1,dir:input;\r
+REFPOS,dir:input;\r
+STROBE,dir:input;\r
+PWM,dir:input;\r
+TRINT,dir:input;\r
+DRVB,dir:input;\r
+DRVA,dir:input;\r
+EXTINT,dir:input;\r
+BRAKE,dir:input;\r
+PWMEN,dir:input;\r
+D0,dir:input;\r
+!EWR,dir:input;\r
+!ERD,dir:input;\r
+!CSPWM,dir:input;\r
+CSLATCH,dir:input;\r
+AR,dir:input;\r
+SP,dir:input;\r
+AR,dir:output,group:20;\r
+SP,dir:output,group:21;\r
+EXTINT,dir:output,group:7;\r
+Equations\r
+AR =0;\r
+SP =0;\r
+EXTINT=!TRINT;\r
--- /dev/null
+"Place Version: 2.8.2\r
+***********************\r
+* DIP FORMAT ONLY *\r
+***********************\r
+Actuator Interface Card Decoder \r
+Part Number = PEEL22CV10\r
+\r
+PinNode 1 = CLK\r
+PinNode 2 = A19\r
+PinNode 3 = A18\r
+PinNode 4 = A17\r
+PinNode 5 = A16\r
+PinNode 6 = !WR\r
+PinNode 7 = !RD\r
+PinNode 8 = D1\r
+PinNode 9 = REFPOS\r
+PinNode 10 = STROBE\r
+PinNode 11 = PWM\r
+PinNode 13 = TRINT\r
+PinNode 14 = DRVB\r
+PinNode 15 = DRVA\r
+PinNode 16 = EXTINT\r
+PinNode 17 = BRAKE\r
+PinNode 18 = PWMEN\r
+PinNode 19 = D0\r
+PinNode 20 = !EWR\r
+PinNode 21 = !ERD\r
+PinNode 22 = !CSPWM\r
+PinNode 23 = CSLATCH\r
+PinNode 25 = AR\r
+PinNode 26 = SP\r
--- /dev/null
+PALASM4 PLDSIM - MARKET RELEASE 1.5 (7-10-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+PALASM SIMULATION HISTORY LISTING\r
+\r
+Title : DECODER.PDS Author : Walter Fetter Lag\r
+Pattern : A Company : UFRGS \r
+Revision : 1.0 Date : 10/10/02 \r
+\r
+PAL22V10 \r
+Page : 1 \r
+ gggggggggggggggggggggggggggggggggggggggggggggggggggggggggggg\r
+ CLOCK LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ A[19] LLLLLLLLLLLHHHHHHHHLLLLLLLLHHHHHHHHLLLLLLLLHHHHHHHHLLLLLLLLH\r
+ A[18] LLLLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHL\r
+ A[17] LLLLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHL\r
+ A[16] LLLLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHL\r
+/WR LLLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLL\r
+/RD LLLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLHHHHHHHHH\r
+ D1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ REFPOS LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHH\r
+/STROBE LLLHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ PWM LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ GND LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ TRINT LHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ DRVB LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ DRVA LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+/EXTINT HLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH\r
+/BRAKE HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH\r
+ PWMEN LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ D0 ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZHZZZZZZZZZZZZZZ\r
+/EWR HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH\r
+/ERD HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLHHHHHHHHHHHHHHH\r
+/CSPWM HHHHHHHHHHHHHHHHHHHHHHHHHHHLHHHHHHHHHHHHHHHLHHHHHHHHHHHHHHHL\r
+/CSLATCH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH\r
+ VCC HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH\r
+\f\r
+PAL22V10 \r
+Page : 2 \r
+ ggggggggggggc gc gc gc pggpgg \r
+ CLOCK LLLLLLLLLLLLHHLLHHLLHHLLHHLLLLLLL \r
+ A[19] HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+ A[18] LLLHHHHHLLLLLLLLLLLLLLLLLLLLLLLLL \r
+ A[17] LHHLLHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+ A[16] HLHLHLHHLLLLLLLLLLLLLLLLLLLLLLLLL \r
+/WR LLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/RD HHHHHHHHLLHHHHHHHHHHHHHHHHHHHHHHH \r
+ D1 LLLLLLLLLLLHHHHLLLLLLLLLLLLLLLLLL \r
+ REFPOS HHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLL \r
+/STROBE LLLLLLLHLLHHHHHHHHHHHHHHHHHHHHHHH \r
+ PWM LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHLH \r
+ GND LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL \r
+ TRINT LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL \r
+ DRVB LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLH \r
+ DRVA LLLLLLLLLLLLLXXXXXXXXHHHHLLLLLLHL \r
+/EXTINT HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/BRAKE HHHHHHHHHHHHHLLLLHHHHHHHHHHHHHHHH \r
+ PWMEN LLLLLLLLLLLLLXXXXXXXXHHHHLLLLLHHH \r
+ D0 ZZZZZZZZHLZZZZZZZZZHHHHLLLLLLLLLL \r
+/EWR LHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/ERD HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/CSPWM HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/CSLATCH HLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+ VCC HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+\f\r
--- /dev/null
+\r
+PALASM4 PAL ASSEMBLER - MARKET RELEASE 1.5a (8-20-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+\r
+TITLE :DECODER.PDS AUTHOR :Walter Fetter Lages \r
+PATTERN :A COMPANY:UFRGS \r
+REVISION:1.0 DATE :10/10/02 \r
+\r
+\ 2\r
+PAL22V10\r
+DECODER*\r
+QV0085*\r
+QP24*\r
+QF5828*\r
+G0*F0*\r
+L0000 00000000000000000000000000000000000000000000*\r
+L0044 11111111111111111111111111111111111111111111*\r
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+L5808 01010101111000011111*\r
+X0*\r
+V0001 0XXXXXXXXXXNXLLHHLZHHHHN*\r
+V0002 0XXXXXXXXXXN1LLLHLZHHHHN*\r
+V0003 0XXXXXXXXXXN0LLHHLZHHHHN*\r
+V0004 0000011XX1XN0LLHHLZHHHHN*\r
+V0005 0000111XX1XN0LLHHLZHHHHN*\r
+V0006 0001011XX1XN0LLHHLZHHHHN*\r
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+V0011 0011111XX1XN0LLHHLZHHHHN*\r
+V0012 0100011XX1XN0LLHHLZHHHHN*\r
+V0013 0100111XX1XN0LLHHLZHHHHN*\r
+V0014 0101011XX1XN0LLHHLZHHHHN*\r
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+V0017 0110111XX1XN0LLHHLZHHHHN*\r
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+V0033 0110111XX0XN0LLHHLZHHHHN*\r
+V0034 0111011XX0XN0LLHHLZHHHHN*\r
+V0035 0111111XX0XN0LLHHLZHHHHN*\r
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+V0037 0000110XX0XN0LLHHLZHHHHN*\r
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+V0049 0110110X10XN0LLHHLZHHHHN*\r
+V0050 0111010X10XN0LLHHLZHHHHN*\r
+V0051 0111110X10XN0LLHHLZHHHHN*\r
+V0052 0000001X10XN0LLHHLZHHHHN*\r
+V0053 0000101X10XN0LLHHLZHHHHN*\r
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+V0055 0001101X10XN0LLHHLZHHHHN*\r
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+V0057 0010101X10XN0LLHHLZHHHHN*\r
+V0058 0011001X10XN0LLHHLZHHHHN*\r
+V0059 0011101X10XN0LLHHLZHHHHN*\r
+V0060 0100001X10XN0LLHHLZHHLHN*\r
+V0061 0100101X10XN0LLHHLZLHHHN*\r
+V0062 0101001X10XN0LLHHLZHHHLN*\r
+V0063 0101101X10XN0LLHHLZHHHHN*\r
+V0064 0110001X10XN0LLHHLZHHHHN*\r
+V0065 0110101X10XN0LLHHLZHHHHN*\r
+V0066 0111001X10XN0LLHHLZHHHHN*\r
+V0067 0111101X10XN0LLHHLZHHHHN*\r
+V0068 0111111X11XN0LLHHLZHHHHN*\r
+V0069 0101010X10XN0LLHHLHHHHHN*\r
+V0070 0101010X00XN0LLHHLLHHHHN*\r
+V0071 0101011X01XN0LLHHLZHHHHN*\r
+V0072 0101011101XN0LLHHLZHHHHN*\r
+V0073 C101011101XN0LXHLXZHHHHN*\r
+V0074 0101011001XN0LXHLXZHHHHN*\r
+V0075 C101011001XN0LXHHXZHHHHN*\r
+V0076 0101011001XN0LXHHX1HHHHN*\r
+V0077 C101011001XN0LHHHH1HHHHN*\r
+V0078 0101011001XN0LHHHH0HHHHN*\r
+V0079 C101011001XN0LLHHL0HHHHN*\r
+V0080 P1010110010N0XXXX10XXXXN*\r
+V0081 01010110010N0LLHHL0HHHHN*\r
+V0082 01010110011N0LLHHL0HHHHN*\r
+V0083 P1010110011N0XXXX00XXXXN*\r
+V0084 01010110010N0LHHHH0HHHHN*\r
+V0085 01010110011N0HLHHH0HHHHN*\r
+C6C0E*\r
+\ 3A8AD\r
--- /dev/null
+\r
+PALASM4 PAL ASSEMBLER - MARKET RELEASE 1.5a (8-20-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+\r
+TITLE :DECODER.PDS AUTHOR :Walter Fetter Lages \r
+PATTERN :A COMPANY:UFRGS \r
+REVISION:1.0 DATE :10/10/02 \r
+\r
+\ 2\r
+PAL22V10\r
+DECODER*\r
+QP24*\r
+QF5828*\r
+G0*F0*\r
+L0000 00000000000000000000000000000000000000000000*\r
+L0044 11111111111111111111111111111111111111111111*\r
+L0088 11110111101101111011101111111111111110111111*\r
+L0132 00000000000000000000000000000000000000000000*\r
+L0176 00000000000000000000000000000000000000000000*\r
+L0220 00000000000000000000000000000000000000000000*\r
+L0264 00000000000000000000000000000000000000000000*\r
+L0308 00000000000000000000000000000000000000000000*\r
+L0352 00000000000000000000000000000000000000000000*\r
+L0396 00000000000000000000000000000000000000000000*\r
+L0440 11111111111111111111111111111111111111111111*\r
+L0484 11110111101110111011111111111111111110111111*\r
+L0528 00000000000000000000000000000000000000000000*\r
+L0572 00000000000000000000000000000000000000000000*\r
+L0616 00000000000000000000000000000000000000000000*\r
+L0660 00000000000000000000000000000000000000000000*\r
+L0704 00000000000000000000000000000000000000000000*\r
+L0748 00000000000000000000000000000000000000000000*\r
+L0792 00000000000000000000000000000000000000000000*\r
+L0836 00000000000000000000000000000000000000000000*\r
+L0880 00000000000000000000000000000000000000000000*\r
+L0924 11111111111111111111111111111111111111111111*\r
+L0968 11110111101110110111111110111111111110111111*\r
+L1012 00000000000000000000000000000000000000000000*\r
+L1056 00000000000000000000000000000000000000000000*\r
+L1100 00000000000000000000000000000000000000000000*\r
+L1144 00000000000000000000000000000000000000000000*\r
+L1188 00000000000000000000000000000000000000000000*\r
+L1232 00000000000000000000000000000000000000000000*\r
+L1276 00000000000000000000000000000000000000000000*\r
+L1320 00000000000000000000000000000000000000000000*\r
+L1364 00000000000000000000000000000000000000000000*\r
+L1408 00000000000000000000000000000000000000000000*\r
+L1452 00000000000000000000000000000000000000000000*\r
+L1496 11111111111111111111111111111111111111111111*\r
+L1540 11110111101110110111101111111111111110111111*\r
+L1584 00000000000000000000000000000000000000000000*\r
+L1628 00000000000000000000000000000000000000000000*\r
+L1672 00000000000000000000000000000000000000000000*\r
+L1716 00000000000000000000000000000000000000000000*\r
+L1760 00000000000000000000000000000000000000000000*\r
+L1804 00000000000000000000000000000000000000000000*\r
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+L1936 00000000000000000000000000000000000000000000*\r
+L1980 00000000000000000000000000000000000000000000*\r
+L2024 00000000000000000000000000000000000000000000*\r
+L2068 00000000000000000000000000000000000000000000*\r
+L2112 00000000000000000000000000000000000000000000*\r
+L2156 11110111101101111011111110111111111110111111*\r
+L2200 11111111111111111111111111111111011111111111*\r
+L2244 00000000000000000000000000000000000000000000*\r
+L2288 00000000000000000000000000000000000000000000*\r
+L2332 00000000000000000000000000000000000000000000*\r
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+L2904 11111111111111111111111111111111111111111111*\r
+L2948 11111111111111111101111111111111111111111111*\r
+L2992 00000000000000000000000000000000000000000000*\r
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+L3608 00000000000000000000000000000000000000000000*\r
+L3652 11111111111111111111111111111111111111111111*\r
+L3696 11111111111111111111111111110111111111111111*\r
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+L4268 00000000000000000000000000000000000000000000*\r
+L4312 11111111111111111111111111111111111111111111*\r
+L4356 11111111111111111111111111111111111111111101*\r
+L4400 00000000000000000000000000000000000000000000*\r
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+L4884 11111111111111111111111111111111111111111111*\r
+L4928 11111111111111111111111011111111111111111011*\r
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+L5324 00000000000000000000000000000000000000000000*\r
+L5368 11111111111111111111111111111111111111111111*\r
+L5412 11111111111111111111111011111111111111110111*\r
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+L5808 01010101111000011111*\r
+C6C0E*\r
+\ 317B8\r
--- /dev/null
+\r
+;PALASM Design Description\r
+\r
+;---------------------------------- Declaration Segment ------------\r
+TITLE DECODER.PDS\r
+PATTERN A\r
+REVISION 1.0\r
+AUTHOR Walter Fetter Lages\r
+COMPANY UFRGS\r
+DATE 10/10/02\r
+\r
+CHIP DECODER PAL22V10\r
+\r
+;---------------------------------- PIN Declarations ---------------\r
+PIN 1 CLOCK ; INPUT\r
+PIN 2..5 A[19..16] ; INPUT\r
+PIN 6 /WR ; INPUT\r
+PIN 7 /RD ; INPUT\r
+PIN 8 D1 ; INPUT\r
+PIN 9 REFPOS ; INPUT\r
+PIN 10 /STROBE ; INPUT\r
+PIN 11 PWM ; INPUT\r
+PIN 12 GND \r
+PIN 13 TRINT ; INPUT\r
+PIN 14 DRVB COMBINATORIAL ; OUTPUT\r
+PIN 15 DRVA COMBINATORIAL ; OUTPUT\r
+PIN 16 /EXTINT COMBINATORIAL ; OUTPUT\r
+PIN 17 /BRAKE REGISTERED ; OUTPUT\r
+PIN 18 PWMEN REGISTERED ; OUTPUT\r
+PIN 19 D0 COMBINATORIAL ; I/O\r
+PIN 20 /EWR COMBINATORIAL ; OUTPUT\r
+PIN 21 /ERD COMBINATORIAL ; OUTPUT\r
+PIN 22 /CSPWM COMBINATORIAL ; OUTPUT\r
+PIN 23 /CSLATCH COMBINATORIAL ; OUTPUT\r
+PIN 24 VCC \r
+\r
+\r
+;----------------------------------- Boolean Equation Segment ------\r
+EQUATIONS\r
+\r
+EXTINT = TRINT\r
+\r
+CSPWM= STROBE * A[19] * /A[18] * /A[17] * /A[16] \r
+ERD= STROBE * RD * A[19] * /A[18] * /A[17] * A[16] \r
+EWR= STROBE * WR * A[19] * /A[18] * /A[17] * A[16] \r
+CSLATCH= STROBE * WR * A[19] * /A[18] * A[17] * /A[16] \r
+\r
+D0.TRST= STROBE * RD * A[19] * /A[18] * A[17] * /A[16]\r
+D0=REFPOS\r
+PWMEN=D0\r
+\r
+BRAKE=D1\r
+\r
+DRVA=PWMEN * /PWM\r
+DRVB=PWMEN * PWM\r
+\r
+;----------------------------------- State Segment -----------------\r
+STATE\r
+\r
+CLKF = CLOCK\r
+\r
+;----------------------------------- Simulation Segment ------------\r
+SIMULATION\r
+\r
+SETF /CLOCK\r
+\r
+; TRINT/EXTINT tests\r
+\r
+TRACE_ON TRINT EXTINT\r
+SETF TRINT\r
+CHECK EXTINT\r
+SETF /TRINT\r
+CHECK /EXTINT\r
+TRACE_OFF\r
+\r
+; Address decoding tests\r
+\r
+TRACE_ON A[19..16] /STROBE /RD /WR /CSPWM /ERD /EWR /CSLATCH D0\r
+\r
+SETF /A[19] /A[18] /A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] /A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+\r
+SETF /A[19] /A[18] /A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] /A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] /A[16] STROBE /RD /WR\r
+CHECK CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+\r
+SETF /A[19] /A[18] /A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] /A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] /A[16] STROBE RD /WR ; CSPWM active\r
+CHECK CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] A[16] STROBE RD /WR ; ERD active\r
+CHECK /CSPWM ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] /A[16] STROBE RD /WR REFPOS ; DO driving output\r
+CHECK /CSPWM /ERD /EWR /CSLATCH D0\r
+SETF A[19] /A[18] A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+\r
+SETF /A[19] /A[18] /A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] /A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] /A[16] STROBE /RD WR\r
+CHECK CSPWM /ERD /EWR /CSLATCH ^D0 ; CSPWM active\r
+SETF A[19] /A[18] /A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD EWR /CSLATCH ^D0 ; EWR active\r
+SETF A[19] /A[18] A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR CSLATCH ^D0 ; CSLATCH active\r
+SETF A[19] /A[18] A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /STROBE /RD /WR\r
+\r
+TRACE_OFF\r
+\r
+; REFPOS tests\r
+\r
+TRACE_ON A[19..16] /STROBE /RD /WR /CSPWM /ERD /EWR /CSLATCH D0 REFPOS\r
+\r
+SETF A[19] /A[18] A[17] /A[16] STROBE RD /WR REFPOS\r
+CHECK /CSPWM /ERD /EWR /CSLATCH D0\r
+SETF A[19] /A[18] A[17] /A[16] STROBE RD /WR /REFPOS\r
+CHECK /CSPWM /ERD /EWR /CSLATCH /D0 \r
+SETF /STROBE /RD /WR\r
+\r
+TRACE_OFF\r
+\r
+; BRAKE/D1 tests\r
+\r
+TRACE_ON CLOCK D1 BRAKE\r
+\r
+SETF D1\r
+CLOCKF CLOCK\r
+CHECK BRAKE\r
+SETF /D1\r
+CLOCKF CLOCK\r
+CHECK /BRAKE\r
+\r
+TRACE_OFF\r
+\r
+; PWMEN/D0 tests\r
+\r
+TRACE_ON CLOCK D0 PWMEN\r
+\r
+SETF D0\r
+CLOCKF CLOCK\r
+CHECK PWMEN\r
+SETF /D0\r
+CLOCKF CLOCK\r
+CHECK /PWMEN\r
+\r
+TRACE_OFF\r
+\r
+; DRVA/DRVB/PWM tests\r
+\r
+TRACE_ON PWMEN PWM DRVA DRVB\r
+\r
+PRELOAD /PWMEN\r
+SETF /PWM\r
+CHECK /DRVA /DRVB\r
+SETF PWM\r
+CHECK /DRVA /DRVB\r
+\r
+PRELOAD PWMEN\r
+SETF /PWM\r
+CHECK DRVA /DRVB\r
+SETF PWM\r
+CHECK /DRVA DRVB\r
+\r
+TRACE_OFF\r
+\r
+;-------------------------------------------------------------------\r
+\r
+\r
--- /dev/null
+TITLE: DECODER.PDS\r
+PATTERN: A\r
+REVISION: 1.0\r
+AUTHOR: Walter Fetter Lages\r
+COMPANY: UFRGS\r
+DATE: 10/10/02\r
+MACRO: DECODER\r
+ PAL22V10\r
+ ÉÍÍÍÍÉ»ÍÍÍÍ»\r
+ CLOCK É͹ 1 ȼ 24 ÌÍ» VCC \r
+ A[19] É͹ 2 23 ÌÍ» /CSLATCH COM \r
+ A[18] É͹ 3 22 ÌÍ» /CSPWM COM \r
+ A[17] É͹ 4 21 ÌÍ» /ERD COM \r
+ A[16] É͹ 5 20 ÌÍ» /EWR COM \r
+ /WR É͹ 6 19 ÌÍ» D0 COM \r
+ /RD É͹ 7 18 ÌÍ» PWMEN REG \r
+ D1 É͹ 8 17 ÌÍ» /BRAKE REG \r
+ REFPOS É͹ 9 16 ÌÍ» /EXTINT COM \r
+ /STROBE É͹ 10 15 ÌÍ» DRVA COM \r
+ PWM É͹ 11 14 ÌÍ» DRVB COM \r
+ GND É͹ 12 13 ÌÍ» TRINT \r
+ ÈÍÍÍÍÍÍÍÍÍͼ\r
--- /dev/null
+TITLE 'Actuator Interface Card Decoder '\r
+DESIGNER 'Walter Fetter Lages '\r
+DATE 'October, 11 2002 '\r
+\r
+Description\r
+ This is the decoder for the Actuator Interface Card. It' main purpose is to decode the addresses\r
+ from TINI and generate the control signals for the chips connected to TINI bus (8254 and HCTL-2016).\r
+ However it is also used for other purposes:\r
+ 1) generate the driving signals to the mosfet motor driver (maps PWM to DRVA and DRVB)\r
+ 2) invert the interrupt request from 8254 (maps TRINT to EXTINT)\r
+ 3) generate the driving signal to the mosfet breake driver (latched output contoled by D0)\r
+ 4) read the reference position sensor (REFPOS is tri-stated and output to D0)\r
+End_Desc;\r
+\r
+PEEL22CV10A\r
+\r
+CLK pin 1\r
+A19 Pin 2 \r
+A18 Pin 3 \r
+A17 Pin 4 \r
+A16 Pin 5 \r
+/WR Pin 6 \r
+/RD Pin 7 \r
+D1 Pin 8 \r
+REFPOS Pin 9 \r
+STROBE Pin 10 \r
+PWM Pin 11 \r
+TRINT Pin 13 \r
+\r
+\r
+"I/O CONFIGURATION DECLARATION\r
+"IOC (PIN_NO 'PIN_NAME' POLARITY OUTPUT_TYPE FEEDBACK_TYPE )\r
+ IOC ( 14 'DRVB' Pos OutCom Feed_Pin )\r
+ IOC ( 15 'DRVA' Pos OutCom Feed_Pin )\r
+ IOC ( 16 'EXTINT' Pos OutCom Feed_Pin )\r
+ IOC ( 17 'BRAKE' Pos Reg Feed_Reg )\r
+ IOC ( 18 'PWMEN' Pos OutReg Feed_Reg )\r
+ IOC ( 19 'D0' Pos Com Feed_Pin )\r
+ IOC ( 20 '/EWR' Pos OutCom Feed_Pin )\r
+ IOC ( 21 '/ERD' Pos OutCom Feed_Pin )\r
+ IOC ( 22 '/CSPWM' Pos OutCom Feed_Pin )\r
+ IOC ( 23 'CSLATCH' Pos OutCom Feed_Pin )\r
+\r
+AR NODE 25 "Global Asynchronous Reset\r
+SP NODE 26 "Global Synchronous Preset\r
+\r
+DEFINE\r
+\r
+\r
+EQUATIONS\r
+\r
+AR = 0;\r
+\r
+SP = 0;\r
+\r
+"All Equations must end with semicolons.\r
+"Internal or External output names appended with extensions:\r
+" 1) .COM for Combinatorial Output\r
+" 2) .D for D-type Registered Output\r
+" 3) .OE for Output Enable Control\r
+\r
+EXTINT=!TRINT\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+PALASM4 PLDSIM - MARKET RELEASE 1.5 (7-10-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+PALASM SIMULATION SELECTIVE TRACE LISTING\r
+\r
+Title : DECODER.PDS Author : Walter Fetter Lag\r
+Pattern : A Company : UFRGS \r
+Revision : 1.0 Date : 10/10/02 \r
+\r
+PAL22V10 \r
+Page : 1 \r
+\v\r
+ gg \r
+ TRINT HL \r
+ EXTINT HL \r
+\f\r
+PAL22V10 \r
+Page : 2 \r
+\v\r
+ gggggggggggggggggggggggggggggggggggggggggggggggggggggggggggg\r
+ A[19] LLLLLLLLHHHHHHHHLLLLLLLLHHHHHHHHLLLLLLLLHHHHHHHHLLLLLLLLHHHH\r
+ A[18] LLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLL\r
+ A[17] LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH\r
+ A[16] LHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLH\r
+/STROBE HHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+/RD HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLHHHHHHHHHHHH\r
+/WR HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLL\r
+/CSPWM HHHHHHHHHHHHHHHHHHHHHHHHLHHHHHHHHHHHHHHHLHHHHHHHHHHHHHHHLHHH\r
+/ERD HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLHHHHHHHHHHHHHHHHHH\r
+/EWR HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLHH\r
+/CSLATCH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLH\r
+ D0 ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZHZZZZZZZZZZZZZZZZZ\r
+\f\r
+PAL22V10 \r
+Page : 3 \r
+ ggggg \r
+ A[19] HHHHH \r
+ A[18] HHHHH \r
+ A[17] LLHHH \r
+ A[16] LHLHH \r
+/STROBE LLLLH \r
+/RD HHHHH \r
+/WR LLLLH \r
+/CSPWM HHHHH \r
+/ERD HHHHH \r
+/EWR HHHHH \r
+/CSLATCH HHHHH \r
+ D0 ZZZZZ \r
+\f\r
+PAL22V10 \r
+Page : 4 \r
+\v\r
+ ggg \r
+ A[19] HHH \r
+ A[18] LLL \r
+ A[17] HHH \r
+ A[16] LLL \r
+/STROBE LLH \r
+/RD LLH \r
+/WR HHH \r
+/CSPWM HHH \r
+/ERD HHH \r
+/EWR HHH \r
+/CSLATCH HHH \r
+ D0 HLZ \r
+ REFPOS HLL \r
+\f\r
+PAL22V10 \r
+Page : 5 \r
+\v\r
+ gc gc \r
+ CLOCK LHHLLHHL \r
+ D1 HHHHLLLL \r
+ BRAKE LLHHHHLL \r
+\f\r
+PAL22V10 \r
+Page : 6 \r
+\v\r
+ gc gc \r
+ CLOCK LHHLLHHL \r
+ D0 HHHHLLLL \r
+ PWMEN XXHHHHLL \r
+\f\r
+PAL22V10 \r
+Page : 7 \r
+\v\r
+ pggpgg \r
+ PWMEN LLLHHH \r
+ PWM LLHHLH \r
+ DRVA LLLLHL \r
+ DRVB LLLLLH \r
+\f\r
--- /dev/null
+ gggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggg\r
+ CLOCK ¿ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ A[19] ¿ ÚÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄ¿ ÚÄÄÄÄ\r
+ ÀÄÄÄÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÙ \r
+ A[18] ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ Ú\r
+ ÀÄÄÄÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ\r
+ A[17] ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿\r
+ ÀÄÄÄÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ À\r
+ A[16] ¿ Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿\r
+ ÀÄÄÄÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀ\r
+/WR ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ \r
+ ÀÄÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄ\r
+/RD ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ ÀÄÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ \r
+ D1 ¿ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ REFPOS ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ \r
+/STROBE ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ \r
+ ÀÄÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ PWM ¿ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ TRINT ¿Ú¿ \r
+ ÀÙÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ DRVB ¿ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ DRVA ¿ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+/EXTINT Ú¿ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ ÙÀÙ \r
+/BRAKE ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ Ù \r
+ PWMEN ¿ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ D0 ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZÚZZZZZZZZZZZZZZ\r
+ Ù \r
+/EWR ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ Ù \r
+/ERD ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ Ù ÀÙ \r
+/CSPWM ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿\r
+ Ù ÀÙ ÀÙ À\r
+/CSLATCH ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ Ù \r
+\f\r
+ggggggggc gc gc gc pggpgg\r
+ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ \r
+ÄÄÄÄÄÄÄÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÄÄÄÄÄ\r
+ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ \r
+ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ \r
+ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ÄÙ \r
+Ú¿ÚÄ¿ \r
+ÙÀÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ÄÄÄÙ \r
+ÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ ÀÄÙ \r
+ ÚÄÄÄ¿ \r
+ÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ÄÄÄÄÄ¿ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ Ú¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ÄÄÄÙÀÄÙ \r
+ ÚÄ¿Ú\r
+ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ÀÙ\r
+ \r
+ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ Ú\r
+ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ\r
+ ÚÄÄÄ¿ Ú¿\r
+ÄÄÄÄÄÄÄÄÄXXXXXXXXÙ ÀÄÄÄÄÄÙÀ\r
+ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ \r
+ÄÄÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ ÀÄÄÄÙ \r
+ ÚÄÄÄ¿ ÚÄÄ\r
+ÄÄÄÄÄÄÄÄÄXXXXXXXXÙ ÀÄÄÄÄÙ \r
+ZZZZÄ¿ ÚÄÄÄ¿ \r
+ ÀZZZZZZZZZÙ ÀÄÄÄÄÄÄÄÄÄ\r
+¿ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ÀÙ \r
+ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ \r
+ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+Ù \r
+Ä¿ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ\r
+ ÀÙ \r
+\f\r
--- /dev/null
+ gg#gggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggg\r
+ TRINT ڿ# \r
+ ÙÀ# Z\r
+ EXTINT Ú¿# Ú\r
+ ÙÀ# Ù\r
+ A[19] #¿ ÚÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄ¿ ÚÄÄÄ#Ä\r
+ #ÀÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÙ # \r
+ A[18] #¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ ÚÄÄÄ¿ #Ú\r
+ #ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄÙ ÀÄÄÄ#Ù\r
+ A[17] #¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ¿ ÚÄ#Ä\r
+ #ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ ÀÄÙ # \r
+ A[16] #¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú¿Ú#¿\r
+ #ÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙÀÙ#À\r
+/STROBE #ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ # \r
+ #Ù ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ#Ä\r
+/RD #ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄ#¿\r
+ #Ù ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ #À\r
+/WR #ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ #Ú\r
+ #Ù ÀÄÄÄÄÄÄÄÄÄÄÄ#Ù\r
+/CSPWM #ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄ#Ä\r
+ #Ù ÀÙ ÀÙ # \r
+/ERD #ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ÚÄÄÄÄÄÄÄÄÄÄÄÄÄ#Ä\r
+ #Ù ÀÙ # \r
+/EWR #ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ#Ä\r
+ #Ù # \r
+/CSLATCH #ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ#Ä\r
+ #Ù # \r
+ D0 #ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZÚZZZZZZZZZZZZZ#Ä\r
+ # Ù # \r
+ REFPOS #Ú\r
+ #Ù\r
+ CLOCK \r
+ \r
+ D1 \r
+ \r
+ BRAKE \r
+ \r
+ PWMEN \r
+ \r
+ PWM \r
+ \r
+ DRVA \r
+ \r
+ DRVB \r
+ \r
+\f\r
+ggg#ggg#gc gc #gc gc #pggpgg\r
+ # # # # \r
+ZZZ# # # # \r
+ÄÄÄ# # # # \r
+ # # # # \r
+ÄÄ# # # \r
+ # # # \r
+ÄÄ# # # \r
+ # # # \r
+ÄÄ# # # \r
+ # # # \r
+ # # # \r
+ÄÄ# # # \r
+ Ú# # # \r
+ÄÙ# # # \r
+ Ú# # # \r
+ÄÙ# # # \r
+ÄÄ# # # \r
+ # # # \r
+ÄÄ# # # \r
+ # # # \r
+ÄÄ# # # \r
+ # # # \r
+ÄÄ# # # \r
+ # # # \r
+ÄÄ# # # \r
+ # # # \r
+¿ # #ÚÄÄÄ¿ # \r
+ÀZ# #Ù ÀÄÄÄ# \r
+¿ # # # \r
+ÀÄ# # # \r
+ #¿ÚÄ¿ ÚÄ¿# ÚÄ¿ ÚÄ¿# \r
+ #ÀÙ ÀÄÙ À#ÄÙ ÀÄÙ À# \r
+ #ÚÄÄÄ¿ # # \r
+ #Ù ÀÄÄÄ# # \r
+ #¿ ÚÄÄÄ¿ # # \r
+ #ÀÄÙ ÀÄ# # \r
+ #XXÚÄÄÄ¿ # ÚÄÄ \r
+ # Ù ÀÄ#ÄÄÄÙ \r
+ #¿ ÚÄ¿Ú \r
+ #ÀÄÙ ÀÙ \r
+ #¿ Ú¿ \r
+ #ÀÄÄÄÙÀ \r
+ #¿ Ú \r
+ #ÀÄÄÄÄÙ \r
+\f\r
--- /dev/null
+\r
+PALASM4 PAL ASSEMBLER - MARKET RELEASE 1.5a (8-20-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+\r
+TITLE :DECODER.PDS AUTHOR :Walter Fetter Lages \r
+PATTERN :A COMPANY:UFRGS \r
+REVISION:1.0 DATE :10/10/02 \r
+\r
+PAL22V10\r
+DECODER\r
+\r
+ 11 1111 1111 2222 2222 2233 3333 3333 4444 \r
+ 0123 4567 8901 2345 6789 0123 4567 8901 2345 6789 0123 \r
+\r
+0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+1 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
+2 ---- X--- -X-- X--- -X-- -X-- ---- ---- ---- -X-- ---- \r
+3 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+4 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+5 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+6 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+7 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+8 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+9 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+10 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
+11 ---- X--- -X-- -X-- -X-- ---- ---- ---- ---- -X-- ---- \r
+12 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+13 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+14 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+15 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+16 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+17 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+18 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+19 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+20 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+21 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
+22 ---- X--- -X-- -X-- X--- ---- -X-- ---- ---- -X-- ---- \r
+23 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+24 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+25 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+26 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+27 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+28 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+29 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+30 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+31 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+32 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+33 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+34 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
+35 ---- X--- -X-- -X-- X--- -X-- ---- ---- ---- -X-- ---- \r
+36 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+37 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+38 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+39 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+40 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+41 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+42 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+43 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+44 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+45 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+46 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+47 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+48 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+49 ---- X--- -X-- X--- -X-- ---- -X-- ---- ---- -X-- ---- \r
+50 ---- ---- ---- ---- ---- ---- ---- ---- X--- ---- ---- \r
+51 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+52 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+53 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+54 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+55 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+56 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+57 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+58 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+59 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+60 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+61 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+62 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+63 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+64 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+65 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+66 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
+67 ---- ---- ---- ---- --X- ---- ---- ---- ---- ---- ---- \r
+68 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+69 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+70 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+71 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+72 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+73 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+74 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+75 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+76 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+77 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+78 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+79 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+80 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+81 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+82 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+83 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
+84 ---- ---- ---- ---- ---- ---- ---- X--- ---- ---- ---- \r
+85 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+86 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+87 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+88 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+89 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+90 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+91 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+92 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+93 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+94 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+95 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+96 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+97 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+98 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
+99 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- --X- \r
+100 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+101 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+102 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+103 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+104 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+105 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+106 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+107 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+108 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+109 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+110 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+111 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
+112 ---- ---- ---- ---- ---- ---X ---- ---- ---- ---- -X-- \r
+113 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+114 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+115 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+116 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+117 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+118 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+119 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+120 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+121 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+122 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
+123 ---- ---- ---- ---- ---- ---X ---- ---- ---- ---- X--- \r
+124 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+125 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+126 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+127 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+128 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+129 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+130 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+131 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+ SUMMARY\r
+ -------\r
+\r
+ OUTPUT PINS: 1111112222\r
+ 4567890123\r
+ POLARITY FUSES: --XX--XXXX\r
+\r
+ OUTPUT PINS: 1111112222\r
+ 4567890123\r
+ REG BYPASS FUSES: ---XX-----\r
+\r
+ TOTAL FUSES BLOWN = 855\r
+\r
--- /dev/null
+PALASM4 PLDSIM - MARKET RELEASE 1.5 (7-10-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+PALASM SIMULATION HISTORY LISTING\r
+\r
+Title : DECODER.PDS Author : Walter Fetter Lag\r
+Pattern : A Company : UFRGS \r
+Revision : 1.0 Date : 10/10/02 \r
+\r
+PAL22V10 \r
+Page : 1 \r
+ gggggggggggggggggggggggggggggggggggggggggggggggggggggggggggg\r
+ CLOCK LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ A[19] LLLLLLLLLLHHHHHHHHLLLLLLLLHHHHHHHHLLLLLLLLHHHHHHHHLLLLLLLLHH\r
+ A[18] LLLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLL\r
+ A[17] LLLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLL\r
+ A[16] LLLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLH\r
+/WR LLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLL\r
+/RD LLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLHHHHHHHHHH\r
+ D1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ REFPOS LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHH\r
+/STROBE LLHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ PWM LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ GND LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ TRINT HLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ DRVB LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ DRVA LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+/EXTINT LHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH\r
+/BRAKE HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH\r
+ PWMEN LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL\r
+ D0 ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZHZZZZZZZZZZZZZZZ\r
+/EWR HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHL\r
+/ERD HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLHHHHHHHHHHHHHHHH\r
+/CSPWM HHHHHHHHHHHHHHHHHHHHHHHHHHLHHHHHHHHHHHHHHHLHHHHHHHHHHHHHHHLH\r
+/CSLATCH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH\r
+ VCC HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH\r
+\f\r
+PAL22V10 \r
+Page : 2 \r
+ gggggggggggc gc gc gc gc ggc g \r
+ CLOCK LLLLLLLLLLLHHLLHHLLHHLLHHLLHHLLLHHLL \r
+ A[19] HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+ A[18] LLHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLL \r
+ A[17] HHLLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+ A[16] LHLHLHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLL \r
+/WR LLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/RD HHHHHHHLLHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+ D1 LLLLLLLLLLHHHHHHHHLLLLLLLLLLLLLLLLLL \r
+ REFPOS HHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLL \r
+/STROBE LLLLLLHLLHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+ PWM LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLH \r
+ GND LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL \r
+ TRINT LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL \r
+ DRVB LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLH \r
+ DRVA LLLLLLLLLLLLLLLLLLLLHHHHLLLLLLLLLHHL \r
+/EXTINT HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/BRAKE HHHHHHHHHHHHLLLLHHHHHHHHHHHHHHHHHHHH \r
+ PWMEN LLLLLLLLLLLLLLLLLLLLHHHHLLLLLLLLLHHH \r
+ D0 ZZZZZZZHLZHHHHLLLLHHHHLLLLLLLLLHHHHH \r
+/EWR HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/ERD HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/CSPWM HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+/CSLATCH LHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+ VCC HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \r
+\f\r
--- /dev/null
+\r
+PALASM4 PAL ASSEMBLER - MARKET RELEASE 1.5a (8-20-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+\r
+TITLE :DECODER.PDS AUTHOR :Walter Fetter Lages \r
+PATTERN :A COMPANY:UFRGS \r
+REVISION:1.0 DATE :10/10/02 \r
+\r
+\ 2\r
+PAL22V10\r
+DECODER*\r
+QV0084*\r
+QP24*\r
+QF5828*\r
+G0*F0*\r
+L0000 00000000000000000000000000000000000000000000*\r
+L0044 11111111111111111111111111111111111111111111*\r
+L0088 11110111101101111011101111111111111110111111*\r
+L0132 00000000000000000000000000000000000000000000*\r
+L0176 00000000000000000000000000000000000000000000*\r
+L0220 00000000000000000000000000000000000000000000*\r
+L0264 00000000000000000000000000000000000000000000*\r
+L0308 00000000000000000000000000000000000000000000*\r
+L0352 00000000000000000000000000000000000000000000*\r
+L0396 00000000000000000000000000000000000000000000*\r
+L0440 11111111111111111111111111111111111111111111*\r
+L0484 11110111101110111011111111111111111110111111*\r
+L0528 00000000000000000000000000000000000000000000*\r
+L0572 00000000000000000000000000000000000000000000*\r
+L0616 00000000000000000000000000000000000000000000*\r
+L0660 00000000000000000000000000000000000000000000*\r
+L0704 00000000000000000000000000000000000000000000*\r
+L0748 00000000000000000000000000000000000000000000*\r
+L0792 00000000000000000000000000000000000000000000*\r
+L0836 00000000000000000000000000000000000000000000*\r
+L0880 00000000000000000000000000000000000000000000*\r
+L0924 11111111111111111111111111111111111111111111*\r
+L0968 11110111101110110111111110111111111110111111*\r
+L1012 00000000000000000000000000000000000000000000*\r
+L1056 00000000000000000000000000000000000000000000*\r
+L1100 00000000000000000000000000000000000000000000*\r
+L1144 00000000000000000000000000000000000000000000*\r
+L1188 00000000000000000000000000000000000000000000*\r
+L1232 00000000000000000000000000000000000000000000*\r
+L1276 00000000000000000000000000000000000000000000*\r
+L1320 00000000000000000000000000000000000000000000*\r
+L1364 00000000000000000000000000000000000000000000*\r
+L1408 00000000000000000000000000000000000000000000*\r
+L1452 00000000000000000000000000000000000000000000*\r
+L1496 11111111111111111111111111111111111111111111*\r
+L1540 11110111101110110111101111111111111110111111*\r
+L1584 00000000000000000000000000000000000000000000*\r
+L1628 00000000000000000000000000000000000000000000*\r
+L1672 00000000000000000000000000000000000000000000*\r
+L1716 00000000000000000000000000000000000000000000*\r
+L1760 00000000000000000000000000000000000000000000*\r
+L1804 00000000000000000000000000000000000000000000*\r
+L1848 00000000000000000000000000000000000000000000*\r
+L1892 00000000000000000000000000000000000000000000*\r
+L1936 00000000000000000000000000000000000000000000*\r
+L1980 00000000000000000000000000000000000000000000*\r
+L2024 00000000000000000000000000000000000000000000*\r
+L2068 00000000000000000000000000000000000000000000*\r
+L2112 00000000000000000000000000000000000000000000*\r
+L2156 11110111101101111011111110111111111110111111*\r
+L2200 11111111111111111111111111111111011111111111*\r
+L2244 00000000000000000000000000000000000000000000*\r
+L2288 00000000000000000000000000000000000000000000*\r
+L2332 00000000000000000000000000000000000000000000*\r
+L2376 00000000000000000000000000000000000000000000*\r
+L2420 00000000000000000000000000000000000000000000*\r
+L2464 00000000000000000000000000000000000000000000*\r
+L2508 00000000000000000000000000000000000000000000*\r
+L2552 00000000000000000000000000000000000000000000*\r
+L2596 00000000000000000000000000000000000000000000*\r
+L2640 00000000000000000000000000000000000000000000*\r
+L2684 00000000000000000000000000000000000000000000*\r
+L2728 00000000000000000000000000000000000000000000*\r
+L2772 00000000000000000000000000000000000000000000*\r
+L2816 00000000000000000000000000000000000000000000*\r
+L2860 00000000000000000000000000000000000000000000*\r
+L2904 11111111111111111111111111111111111111111111*\r
+L2948 11111111111111111101111111111011111111111111*\r
+L2992 11111111111111111111111011110111111111111111*\r
+L3036 00000000000000000000000000000000000000000000*\r
+L3080 00000000000000000000000000000000000000000000*\r
+L3124 00000000000000000000000000000000000000000000*\r
+L3168 00000000000000000000000000000000000000000000*\r
+L3212 00000000000000000000000000000000000000000000*\r
+L3256 00000000000000000000000000000000000000000000*\r
+L3300 00000000000000000000000000000000000000000000*\r
+L3344 00000000000000000000000000000000000000000000*\r
+L3388 00000000000000000000000000000000000000000000*\r
+L3432 00000000000000000000000000000000000000000000*\r
+L3476 00000000000000000000000000000000000000000000*\r
+L3520 00000000000000000000000000000000000000000000*\r
+L3564 00000000000000000000000000000000000000000000*\r
+L3608 00000000000000000000000000000000000000000000*\r
+L3652 11111111111111111111111111111111111111111111*\r
+L3696 11111111111111111101111111110111111111111111*\r
+L3740 11111111111111111111111111101011111111111111*\r
+L3784 00000000000000000000000000000000000000000000*\r
+L3828 00000000000000000000000000000000000000000000*\r
+L3872 00000000000000000000000000000000000000000000*\r
+L3916 00000000000000000000000000000000000000000000*\r
+L3960 00000000000000000000000000000000000000000000*\r
+L4004 00000000000000000000000000000000000000000000*\r
+L4048 00000000000000000000000000000000000000000000*\r
+L4092 00000000000000000000000000000000000000000000*\r
+L4136 00000000000000000000000000000000000000000000*\r
+L4180 00000000000000000000000000000000000000000000*\r
+L4224 00000000000000000000000000000000000000000000*\r
+L4268 00000000000000000000000000000000000000000000*\r
+L4312 11111111111111111111111111111111111111111111*\r
+L4356 11111111111111111111111111111111111111111101*\r
+L4400 00000000000000000000000000000000000000000000*\r
+L4444 00000000000000000000000000000000000000000000*\r
+L4488 00000000000000000000000000000000000000000000*\r
+L4532 00000000000000000000000000000000000000000000*\r
+L4576 00000000000000000000000000000000000000000000*\r
+L4620 00000000000000000000000000000000000000000000*\r
+L4664 00000000000000000000000000000000000000000000*\r
+L4708 00000000000000000000000000000000000000000000*\r
+L4752 00000000000000000000000000000000000000000000*\r
+L4796 00000000000000000000000000000000000000000000*\r
+L4840 00000000000000000000000000000000000000000000*\r
+L4884 11111111111111111111111111111111111111111111*\r
+L4928 11111111111111111111111011111111111111111011*\r
+L4972 00000000000000000000000000000000000000000000*\r
+L5016 00000000000000000000000000000000000000000000*\r
+L5060 00000000000000000000000000000000000000000000*\r
+L5104 00000000000000000000000000000000000000000000*\r
+L5148 00000000000000000000000000000000000000000000*\r
+L5192 00000000000000000000000000000000000000000000*\r
+L5236 00000000000000000000000000000000000000000000*\r
+L5280 00000000000000000000000000000000000000000000*\r
+L5324 00000000000000000000000000000000000000000000*\r
+L5368 11111111111111111111111111111111111111111111*\r
+L5412 11111111111111111111111011111111111111110111*\r
+L5456 00000000000000000000000000000000000000000000*\r
+L5500 00000000000000000000000000000000000000000000*\r
+L5544 00000000000000000000000000000000000000000000*\r
+L5588 00000000000000000000000000000000000000000000*\r
+L5632 00000000000000000000000000000000000000000000*\r
+L5676 00000000000000000000000000000000000000000000*\r
+L5720 00000000000000000000000000000000000000000000*\r
+L5764 00000000000000000000000000000000000000000000*\r
+L5808 01010101111000011111*\r
+X0*\r
+V0001 XXXXXXXXXXXN1LLLHLZHHHHN*\r
+V0002 XXXXXXXXXXXN0LLHHLZHHHHN*\r
+V0003 X000011XX1XN0LLHHLZHHHHN*\r
+V0004 X000111XX1XN0LLHHLZHHHHN*\r
+V0005 X001011XX1XN0LLHHLZHHHHN*\r
+V0006 X001111XX1XN0LLHHLZHHHHN*\r
+V0007 X010011XX1XN0LLHHLZHHHHN*\r
+V0008 X010111XX1XN0LLHHLZHHHHN*\r
+V0009 X011011XX1XN0LLHHLZHHHHN*\r
+V0010 X011111XX1XN0LLHHLZHHHHN*\r
+V0011 X100011XX1XN0LLHHLZHHHHN*\r
+V0012 X100111XX1XN0LLHHLZHHHHN*\r
+V0013 X101011XX1XN0LLHHLZHHHHN*\r
+V0014 X101111XX1XN0LLHHLZHHHHN*\r
+V0015 X110011XX1XN0LLHHLZHHHHN*\r
+V0016 X110111XX1XN0LLHHLZHHHHN*\r
+V0017 X111011XX1XN0LLHHLZHHHHN*\r
+V0018 X111111XX1XN0LLHHLZHHHHN*\r
+V0019 X000011XX0XN0LLHHLZHHHHN*\r
+V0020 X000111XX0XN0LLHHLZHHHHN*\r
+V0021 X001011XX0XN0LLHHLZHHHHN*\r
+V0022 X001111XX0XN0LLHHLZHHHHN*\r
+V0023 X010011XX0XN0LLHHLZHHHHN*\r
+V0024 X010111XX0XN0LLHHLZHHHHN*\r
+V0025 X011011XX0XN0LLHHLZHHHHN*\r
+V0026 X011111XX0XN0LLHHLZHHHHN*\r
+V0027 X100011XX0XN0LLHHLZHHLHN*\r
+V0028 X100111XX0XN0LLHHLZHHHHN*\r
+V0029 X101011XX0XN0LLHHLZHHHHN*\r
+V0030 X101111XX0XN0LLHHLZHHHHN*\r
+V0031 X110011XX0XN0LLHHLZHHHHN*\r
+V0032 X110111XX0XN0LLHHLZHHHHN*\r
+V0033 X111011XX0XN0LLHHLZHHHHN*\r
+V0034 X111111XX0XN0LLHHLZHHHHN*\r
+V0035 X000010XX0XN0LLHHLZHHHHN*\r
+V0036 X000110XX0XN0LLHHLZHHHHN*\r
+V0037 X001010XX0XN0LLHHLZHHHHN*\r
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+V0076 C1010110010N0LHHHH1HHHHN*\r
+V0077 01010110010N0LHHHH0HHHHN*\r
+V0078 C1010110010N0LLHHL0HHHHN*\r
+V0079 01010110010N0LLHHL0HHHHN*\r
+V0080 C1010110010N0LLHHL0HHHHN*\r
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+V0083 C1010110010N0LHHHH1HHHHN*\r
+V0084 01010110011N0HLHHH1HHHHN*\r
+C75EB*\r
+\ 3A8A0\r
--- /dev/null
+\r
+PALASM4 PAL ASSEMBLER - MARKET RELEASE 1.5a (8-20-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+\r
+TITLE :DECODER.PDS AUTHOR :Walter Fetter Lages \r
+PATTERN :A COMPANY:UFRGS \r
+REVISION:1.0 DATE :10/10/02 \r
+\r
+\ 2\r
+PAL22V10\r
+DECODER*\r
+QP24*\r
+QF5828*\r
+G0*F0*\r
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+\ 3180F\r
--- /dev/null
+\r
+;PALASM Design Description\r
+\r
+;---------------------------------- Declaration Segment ------------\r
+TITLE DECODER.PDS\r
+PATTERN A\r
+REVISION 1.0\r
+AUTHOR Walter Fetter Lages\r
+COMPANY UFRGS\r
+DATE 10/10/02\r
+\r
+CHIP DECODER PAL22V10\r
+\r
+;---------------------------------- PIN Declarations ---------------\r
+PIN 1 CLOCK ; INPUT\r
+PIN 2..5 A[19..16] ; INPUT\r
+PIN 6 /WR ; INPUT\r
+PIN 7 /RD ; INPUT\r
+PIN 8 D1 ; INPUT\r
+PIN 9 REFPOS ; INPUT\r
+PIN 10 /STROBE ; INPUT\r
+PIN 11 PWM ; INPUT\r
+PIN 12 GND \r
+PIN 13 TRINT ; INPUT\r
+PIN 14 DRVB COMBINATORIAL ; OUTPUT\r
+PIN 15 DRVA COMBINATORIAL ; OUTPUT\r
+PIN 16 /EXTINT COMBINATORIAL ; OUTPUT\r
+PIN 17 /BRAKE REGISTERED ; OUTPUT\r
+PIN 18 PWMEN REGISTERED ; OUTPUT\r
+PIN 19 D0 COMBINATORIAL ; I/O\r
+PIN 20 /EWR COMBINATORIAL ; OUTPUT\r
+PIN 21 /ERD COMBINATORIAL ; OUTPUT\r
+PIN 22 /CSPWM COMBINATORIAL ; OUTPUT\r
+PIN 23 /CSLATCH COMBINATORIAL ; OUTPUT\r
+PIN 24 VCC \r
+\r
+\r
+;----------------------------------- Boolean Equation Segment ------\r
+EQUATIONS\r
+\r
+EXTINT = TRINT\r
+\r
+CSPWM= STROBE * A[19] * /A[18] * /A[17] * /A[16] \r
+ERD= STROBE * RD * A[19] * /A[18] * /A[17] * A[16] \r
+EWR= STROBE * WR * A[19] * /A[18] * /A[17] * A[16] \r
+CSLATCH= STROBE * WR * A[19] * /A[18] * A[17] * /A[16] \r
+\r
+D0.TRST= STROBE * RD * A[19] * /A[18] * A[17] * /A[16]\r
+D0=REFPOS\r
+
+PWMEN=D0 * /D1 + PWMEN * D1\r
+\r
+BRAKE=D0 * D1 + BRAKE * /D1\r
+\r
+DRVA=PWMEN * /PWM\r
+DRVB=PWMEN * PWM\r
+\r
+;----------------------------------- State Segment -----------------\r
+STATE\r
+\r
+CLKF = CLOCK\r
+\r
+;----------------------------------- Simulation Segment ------------\r
+SIMULATION\r
+\r
+; TRINT/EXTINT tests\r
+\r
+TRACE_ON TRINT EXTINT\r
+SETF TRINT\r
+CHECK EXTINT\r
+SETF /TRINT\r
+CHECK /EXTINT\r
+TRACE_OFF\r
+\r
+; Address decoding tests\r
+\r
+TRACE_ON A[19..16] /STROBE /RD /WR /CSPWM /ERD /EWR /CSLATCH D0\r
+\r
+SETF /A[19] /A[18] /A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] /A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] /A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] A[16] /STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+\r
+SETF /A[19] /A[18] /A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] /A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] /A[16] STROBE /RD /WR\r
+CHECK CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] /A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] A[16] STROBE /RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+\r
+SETF /A[19] /A[18] /A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] /A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] /A[16] STROBE RD /WR ; CSPWM active\r
+CHECK CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] A[16] STROBE RD /WR ; ERD active\r
+CHECK /CSPWM ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] A[17] /A[16] STROBE RD /WR REFPOS ; DO driving output\r
+CHECK /CSPWM /ERD /EWR /CSLATCH D0\r
+SETF A[19] /A[18] A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] /A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] A[16] STROBE RD /WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+\r
+SETF /A[19] /A[18] /A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] /A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] /A[18] A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] /A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /A[19] A[18] A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] /A[18] /A[17] /A[16] STROBE /RD WR\r
+CHECK CSPWM /ERD /EWR /CSLATCH ^D0 ; CSPWM active\r
+SETF A[19] /A[18] /A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD EWR /CSLATCH ^D0 ; EWR active\r
+SETF A[19] /A[18] A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR CSLATCH ^D0 ; CSLATCH active\r
+SETF A[19] /A[18] A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] /A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] /A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF A[19] A[18] A[17] A[16] STROBE /RD WR\r
+CHECK /CSPWM /ERD /EWR /CSLATCH ^D0\r
+SETF /STROBE /RD /WR\r
+\r
+TRACE_OFF\r
+\r
+; REFPOS tests\r
+\r
+TRACE_ON A[19..16] /STROBE /RD /WR /CSPWM /ERD /EWR /CSLATCH D0 REFPOS\r
+\r
+SETF A[19] /A[18] A[17] /A[16] STROBE RD /WR REFPOS\r
+CHECK /CSPWM /ERD /EWR /CSLATCH D0\r
+SETF A[19] /A[18] A[17] /A[16] STROBE RD /WR /REFPOS\r
+CHECK /CSPWM /ERD /EWR /CSLATCH /D0 \r
+SETF /STROBE /RD /WR\r
+\r
+TRACE_OFF\r
+\r
+; BRAKE PWMEN tests\r
+\r
+TRACE_ON CLOCK D0 D1 BRAKE PWMEN\r
+\r
+SETF D0 D1\r
+CLOCKF CLOCK\r
+CHECK BRAKE\r /PWMEN
+SETF /D0 D1\r
+CLOCKF CLOCK\r
+CHECK /BRAKE\r /PWMEN
+\r
+SETF D0 /D1 /PWM\r
+CLOCKF CLOCK\r
+CHECK /BRAKE PWMEN DRVA /DRVB\r
+SETF /D0 /D1 /PWM\r
+CLOCKF CLOCK\r
+CHECK /BRAKE /PWMEN /DRVA /DRVB\r
+\r
+TRACE_OFF\r
+\r
+; DRVA/DRVB/PWM tests\r
+\r
+TRACE_ON PWMEN PWM DRVA DRVB\r
+\r
+SETF /PWM\r /D1 /D0
+CLOCKF CLOCK
+CHECK /DRVA /DRVB /PWMEN\r
+SETF PWM\r
+CHECK /DRVA /DRVB /PWMEN\r
+\r
+SETF /PWM\r /D1 D0
+CLOCKF CLOCK
+CHECK DRVA /DRVB PWMEN\r
+SETF PWM\r
+CHECK /DRVA DRVB PWMEN\r
+\r
+TRACE_OFF\r
+\r
+;-------------------------------------------------------------------\r
+\r
+\r
--- /dev/null
+PALASM4 PLDSIM - MARKET RELEASE 1.5 (7-10-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+PALASM SIMULATION SELECTIVE TRACE LISTING\r
+\r
+Title : DECODER.PDS Author : Walter Fetter Lag\r
+Pattern : A Company : UFRGS \r
+Revision : 1.0 Date : 10/10/02 \r
+\r
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--- /dev/null
+\r
+PALASM4 PAL ASSEMBLER - MARKET RELEASE 1.5a (8-20-92)\r
+ (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992\r
+\r
+\r
+TITLE :DECODER.PDS AUTHOR :Walter Fetter Lages \r
+PATTERN :A COMPANY:UFRGS \r
+REVISION:1.0 DATE :10/10/02 \r
+\r
+PAL22V10\r
+DECODER\r
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+9 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
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+13 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
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+16 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+17 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
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+20 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
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+24 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
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+32 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+33 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
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+41 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+42 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+43 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
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+\r
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+65 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
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+\r
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+96 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+97 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
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+110 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
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+114 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
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+121 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+122 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- \r
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+124 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+125 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+126 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
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+129 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+130 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+131 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX \r
+\r
+ SUMMARY\r
+ -------\r
+\r
+ OUTPUT PINS: 1111112222\r
+ 4567890123\r
+ POLARITY FUSES: --XX--XXXX\r
+\r
+ OUTPUT PINS: 1111112222\r
+ 4567890123\r
+ REG BYPASS FUSES: ---XX-----\r
+\r
+ TOTAL FUSES BLOWN = 937\r
+\r
--- /dev/null
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projects / aic.git / commitdiff
