Reworked source tree.
Capacitor involucre sizes made invisible in schematics.
Created a workaround to fix a incompatibility between pic30-gcc 3.01 and
FreeRTOS. See the hack 1 in the Hacks file.
+2012.04.20 Started aic-2.3.0.
+ Reworked source tree.
+ Capacitor involucre sizes made invisible in schematics.
+ Created a workaround to fix a incompatibility between
+ pic30-gcc 3.01 and FreeRTOS. See the hack 1 in the Hacks
+ file.
+
+2009.02.09 Started aic-2.2.0.
+ aic-2.2.* uses the irs21094 MOSFET driver.
+
+2008.08.26 Started aic-2.1.0.
+ aic-2.1.* uses the LT1162 MOSFET driver.
+
+2006.06.11 Started aic-2.0.0.
+ aic-2.*.* uses the dsPIC30F4012 processor.
+ aic-2.0.* uses the MAX5062 MOSFET driver.
+
2006.06.11 Inicio do projeto aic-2.0.0
2008.02.15 Incluido destrutor virtual na classe AIC_COMM.
Criadas classes HostUDP e HostCAN, derivadas de Host.
+2002.xx.xx Started aic-1.0.0.
+ aic-1.0.0 uses the TINI DS390 processor.
\ No newline at end of file
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) -I. $(CCFLAGS)
daemon:daemon.o
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLDFILE) $(AICLIB)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLD) $(AICLIB)
daemon.hex:daemon
$(CCBIN2HEX) $^
$(CCBIN2HEX) $^
daemonrtos:daemonrtos.o $(OSOBJS)
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLDFILE) $(AICLIB)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLD) $(AICLIB)
daemonrtos.o:daemonrtos.c
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) $(OSINCDIR) $(CCFLAGS) $(OSFLAGS)
--- /dev/null
+1. Imcompatibility between pic30-gcc 3.01 and FreeRTOS 4.7.2 and above
+
+There is an incompatibility between the current pic30-gcc version and the
+FreeRTOS regarding the setting of the prescaler for the T1 timer in
+FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c.
+
+FreeRTOS wants to set the TCKPS0 and TCKPS1 bits as 1-bit fields, while
+pic30-gcc defines in /usr/lib/gcc/pic30-elf/3.01/include/p30f4012.h the
+T1CONbits structure with a 2-bit field named TCKPS.
+
+Since FreeRTOS uses an 8x prescaler (TCKPS0=1, TCKPS1=0 or TCKPS=1), the
+hack is to define -DTCKPS0=TCKPS -DTCKPS1=TSYNC in the compiler options.
+
+Hence the FreeRTOS code:
+
+T1CONbits.TCKPS0 = 1;
+T1CONbits.TCKPS1 = 0;
+
+is seen by the compiler as
+
+T1CONbits.TCKPS = 1;
+T1CONbits.TSYNC = 0;
+
+Note that TSYNC is initialized by the hardware as 0 and is not touched by
+FreeRTOS. Therefore, the above code should be harmless.
+
+-------------------------------------------------------------------------
-export AICROOT=$(HOME)/src/aic
+export AICROOT=$(PWD)
export CC=pic30-elf-gcc
export CCAR=pic30-elf-ar
export CCFLAGS=-Wall -O2 -fomit-frame-pointer -fno-schedule-insns -fno-schedule-insns2
export CPU=-mcpu=30F4012
export CCINCDIR=-I$(AICROOT)/include
-export CCLIBDIR=-L/usr/pic30-elf/
-export CCGLDDIR=$(AICROOT)/gld
-export CCGLDFILE=-T $(CCGLDDIR)/p30f4012.gld
+export CCLIBDIR=
+export CCGLD=-T p30f4012.gld
-export OSROOT=$(AICROOT)/FreeRTOS
-export OSFILES=$(OSROOT)/list.c $(OSROOT)/queue.c $(OSROOT)/tasks.c $(OSROOT)/croutine.c $(OSROOT)/portable/AIC-2.0.0/port.c $(OSROOT)/portable/MemMang/heap_1.c
+export OSROOT=/usr/src/FreeRTOS/Source
+export OSFILES=$(OSROOT)/list.c $(OSROOT)/queue.c $(OSROOT)/tasks.c \
+ $(OSROOT)/croutine.c $(OSROOT)/portable/MPLAB/PIC24_dsPIC/port.c \
+ $(OSROOT)/portable/MemMang/heap_1.c
export OSOBJS=list.o queue.o tasks.o croutine.o port.o heap_1.o
-export OSINCDIR=-I$(OSROOT)/include -I$(OSROOT)/portable/AIC-2.0.0/
-export OSFLAGS=-DAIC_DSPIC_PORT
+export OSINCDIR=-I$(OSROOT)/include -I$(OSROOT)/portable/MPLAB/PIC24_ds_PIC
+export OSFLAGS=-DMPLAB_DSPIC_PORT -DTCKPS0=TCKPS -DTCKPS1=TSYNC
export AICLIBDIR=-L$(AICROOT)/lib
--- /dev/null
+Update freeRTOS.
+++ /dev/null
-size of char... 1
-size of short... 2
-size of int... 2
-size of long... 4
-size of long long... 8
-size of float... 4
-size of double... 4
-int 0x0733 byte[0]:33 byte[1]:7
\ No newline at end of file
--- /dev/null
+# Doxyfile 1.3.7
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project
+#
+# All text after a hash (#) is considered a comment and will be ignored
+# The format is:
+# TAG = value [value, ...]
+# For lists items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ")
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
+# by quotes) that should identify the project.
+
+PROJECT_NAME = "Actuator Interface Card"
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number.
+# This could be handy for archiving the generated documentation or
+# if some version control system is used.
+
+PROJECT_NUMBER = "2.3.0"
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
+# base path where the generated documentation will be put.
+# If a relative path is entered, it will be relative to the location
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY = .
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
+# 2 levels of 10 sub-directories under the output directory of each output
+# format and will distribute the generated files over these directories.
+# Enabling this option can be useful when feeding doxygen a huge amount of source
+# files, where putting all generated files in the same directory would otherwise
+# cause performance problems for the file system.
+
+CREATE_SUBDIRS = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# The default language is English, other supported languages are:
+# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, Dutch,
+# Finnish, French, German, Greek, Hungarian, Italian, Japanese, Japanese-en
+# (Japanese with English messages), Korean, Korean-en, Norwegian, Polish, Portuguese,
+# Romanian, Russian, Serbian, Slovak, Slovene, Spanish, Swedish, and Ukrainian.
+
+OUTPUT_LANGUAGE = English
+
+# This tag can be used to specify the encoding used in the generated output.
+# The encoding is not always determined by the language that is chosen,
+# but also whether or not the output is meant for Windows or non-Windows users.
+# In case there is a difference, setting the USE_WINDOWS_ENCODING tag to YES
+# forces the Windows encoding (this is the default for the Windows binary),
+# whereas setting the tag to NO uses a Unix-style encoding (the default for
+# all platforms other than Windows).
+
+USE_WINDOWS_ENCODING = NO
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
+# include brief member descriptions after the members that are listed in
+# the file and class documentation (similar to JavaDoc).
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
+# the brief description of a member or function before the detailed description.
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator
+# that is used to form the text in various listings. Each string
+# in this list, if found as the leading text of the brief description, will be
+# stripped from the text and the result after processing the whole list, is used
+# as the annotated text. Otherwise, the brief description is used as-is. If left
+# blank, the following values are used ("$name" is automatically replaced with the
+# name of the entity): "The $name class" "The $name widget" "The $name file"
+# "is" "provides" "specifies" "contains" "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF =
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# Doxygen will generate a detailed section even if there is only a brief
+# description.
+
+ALWAYS_DETAILED_SEC = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all inherited
+# members of a class in the documentation of that class as if those members were
+# ordinary class members. Constructors, destructors and assignment operators of
+# the base classes will not be shown.
+
+INLINE_INHERITED_MEMB = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
+# path before files name in the file list and in the header files. If set
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
+# can be used to strip a user-defined part of the path. Stripping is
+# only done if one of the specified strings matches the left-hand part of
+# the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the
+# path to strip.
+
+STRIP_FROM_PATH = ..
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
+# the path mentioned in the documentation of a class, which tells
+# the reader which header file to include in order to use a class.
+# If left blank only the name of the header file containing the class
+# definition is used. Otherwise one should specify the include paths that
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
+# (but less readable) file names. This can be useful is your file systems
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
+# will interpret the first line (until the first dot) of a JavaDoc-style
+# comment as the brief description. If set to NO, the JavaDoc
+# comments will behave just like the Qt-style comments (thus requiring an
+# explicit @brief command for a brief description.
+
+JAVADOC_AUTOBRIEF = YES
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
+# treat a multi-line C++ special comment block (i.e. a block of //! or ///
+# comments) as a brief description. This used to be the default behaviour.
+# The new default is to treat a multi-line C++ comment block as a detailed
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the DETAILS_AT_TOP tag is set to YES then Doxygen
+# will output the detailed description near the top, like JavaDoc.
+# If set to NO, the detailed description appears after the member
+# documentation.
+
+DETAILS_AT_TOP = YES
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
+# member inherits the documentation from any documented member that it
+# re-implements.
+
+INHERIT_DOCS = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES, then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC = YES
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab.
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE = 8
+
+# This tag can be used to specify a number of aliases that acts
+# as commands in the documentation. An alias has the form "name=value".
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to
+# put the command \sideeffect (or @sideeffect) in the documentation, which
+# will result in a user-defined paragraph with heading "Side Effects:".
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources
+# only. Doxygen will then generate output that is more tailored for C.
+# For instance, some of the names that are used will be different. The list
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C = NO
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources
+# only. Doxygen will then generate output that is more tailored for Java.
+# For instance, namespaces will be presented as packages, qualified scopes
+# will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
+# the same type (for instance a group of public functions) to be put as a
+# subgroup of that type (e.g. under the Public Functions section). Set it to
+# NO to prevent subgrouping. Alternatively, this can be done per class using
+# the \nosubgrouping command.
+
+SUBGROUPING = YES
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
+# documentation are documented, even if no documentation was available.
+# Private class members and static file members will be hidden unless
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+
+EXTRACT_ALL = NO
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
+# will be included in the documentation.
+
+EXTRACT_PRIVATE = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file
+# will be included in the documentation.
+
+EXTRACT_STATIC = NO
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
+# defined locally in source files will be included in the documentation.
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES = YES
+
+# This flag is only useful for Objective-C code. When set to YES local
+# methods, which are defined in the implementation section but not in
+# the interface are included in the documentation.
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS = YES
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
+# undocumented members of documented classes, files or namespaces.
+# If set to NO (the default) these members will be included in the
+# various overviews, but no documentation section is generated.
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy.
+# If set to NO (the default) these classes will be included in the various
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
+# friend (class|struct|union) declarations.
+# If set to NO (the default) these declarations will be included in the
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
+# documentation blocks found inside the body of a function.
+# If set to NO (the default) these blocks will be appended to the
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS = NO
+
+# The INTERNAL_DOCS tag determines if documentation
+# that is typed after a \internal command is included. If the tag is set
+# to NO (the default) then the documentation will be excluded.
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
+# file names in lower-case letters. If set to YES upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# users are advised to set this option to NO.
+
+CASE_SENSE_NAMES = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
+# will show members with their full class and namespace scopes in the
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
+# will put a list of the files that are included by a file in the documentation
+# of that file.
+
+SHOW_INCLUDE_FILES = YES
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
+# is inserted in the documentation for inline members.
+
+INLINE_INFO = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
+# will sort the (detailed) documentation of file and class members
+# alphabetically by member name. If set to NO the members will appear in
+# declaration order.
+
+SORT_MEMBER_DOCS = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
+# brief documentation of file, namespace and class members alphabetically
+# by member name. If set to NO (the default) the members will appear in
+# declaration order.
+
+SORT_BRIEF_DOCS = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
+# sorted by fully-qualified names, including namespaces. If set to
+# NO (the default), the class list will be sorted only by class name,
+# not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME = YES
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or
+# disable (NO) the todo list. This list is created by putting \todo
+# commands in the documentation.
+
+GENERATE_TODOLIST = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or
+# disable (NO) the test list. This list is created by putting \test
+# commands in the documentation.
+
+GENERATE_TESTLIST = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or
+# disable (NO) the bug list. This list is created by putting \bug
+# commands in the documentation.
+
+GENERATE_BUGLIST = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
+# disable (NO) the deprecated list. This list is created by putting
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional
+# documentation sections, marked by \if sectionname ... \endif.
+
+ENABLED_SECTIONS =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
+# the initial value of a variable or define consists of for it to appear in
+# the documentation. If the initializer consists of more lines than specified
+# here it will be hidden. Use a value of 0 to hide initializers completely.
+# The appearance of the initializer of individual variables and defines in the
+# documentation can be controlled using \showinitializer or \hideinitializer
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
+# at the bottom of the documentation of classes and structs. If set to YES the
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES = YES
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated by doxygen. Possible values are YES and NO. If left blank
+# NO is used.
+
+WARNINGS = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED = YES
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some
+# parameters in a documented function, or documenting parameters that
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR = YES
+
+# The WARN_FORMAT tag determines the format of the warning messages that
+# doxygen can produce. The string should contain the $file, $line, and $text
+# tags, which will be replaced by the file and line number from which the
+# warning originated and the warning text.
+
+WARN_FORMAT = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning
+# and error messages should be written. If left blank the output is written
+# to stderr.
+
+WARN_LOGFILE =
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain
+# documented source files. You may enter file names like "myfile.cpp" or
+# directories like "/usr/src/myproject". Separate the files or directories
+# with spaces.
+
+INPUT = . \
+ ../include
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank the following patterns are tested:
+# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx *.hpp
+# *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm
+
+FILE_PATTERNS = *.dox *.h *.inc *.java
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories
+# should be searched for input files as well. Possible values are YES and NO.
+# If left blank NO is used.
+
+RECURSIVE = YES
+
+# The EXCLUDE tag can be used to specify files and/or directories that should
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+
+EXCLUDE =
+
+# The EXCLUDE_SYMLINKS tag can be used select whether or not files or directories
+# that are symbolic links (a Unix filesystem feature) are excluded from the input.
+
+EXCLUDE_SYMLINKS = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories.
+
+EXCLUDE_PATTERNS =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or
+# directories that contain example code fragments that are included (see
+# the \include command).
+
+EXAMPLE_PATH =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank all files are included.
+
+EXAMPLE_PATTERNS =
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude
+# commands irrespective of the value of the RECURSIVE tag.
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or
+# directories that contain image that are included in the documentation (see
+# the \image command).
+
+IMAGE_PATH =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command <filter> <input-file>, where <filter>
+# is the value of the INPUT_FILTER tag, and <input-file> is the name of an
+# input file. Doxygen will then use the output that the filter program writes
+# to standard output.
+
+INPUT_FILTER =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will be used to filter the input files when producing source
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will
+# be generated. Documented entities will be cross-referenced with these sources.
+# Note: To get rid of all source code in the generated output, make sure also
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
+# doxygen to hide any special comment blocks from generated source code
+# fragments. Normal C and C++ comments will always remain visible.
+
+STRIP_CODE_COMMENTS = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES (the default)
+# then for each documented function all documented
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = YES
+
+# If the REFERENCES_RELATION tag is set to YES (the default)
+# then for each documented function all documented entities
+# called/used by that function will be listed.
+
+REFERENCES_RELATION = YES
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
+# will generate a verbatim copy of the header file for each class for
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
+# of all compounds will be generated. Enable this if the project
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX = NO
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX = 5
+
+# In case all classes in a project start with a common prefix, all
+# classes will be put under the same header in the alphabetical index.
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
+# generate HTML output.
+
+GENERATE_HTML = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard header.
+
+HTML_HEADER =
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard footer.
+
+HTML_FOOTER =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
+# style sheet that is used by each HTML page. It can be used to
+# fine-tune the look of the HTML output. If the tag is left blank doxygen
+# will generate a default style sheet. Note that doxygen will try to copy
+# the style sheet file to the HTML output directory, so don't put your own
+# stylesheet in the HTML output directory as well, or it will be erased!
+
+HTML_STYLESHEET =
+
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
+# files or namespaces will be aligned in HTML using tables. If set to
+# NO a bullet list will be used.
+
+HTML_ALIGN_MEMBERS = YES
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files
+# will be generated that can be used as input for tools like the
+# Microsoft HTML help workshop to generate a compressed HTML help file (.chm)
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
+# be used to specify the file name of the resulting .chm file. You
+# can add a path in front of the file if the result should not be
+# written to the html output directory.
+
+CHM_FILE =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
+# be used to specify the location (absolute path including file name) of
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
+# controls if a separate .chi index file is generated (YES) or that
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
+# controls whether a binary table of contents is generated (YES) or a
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND = NO
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
+# top of each HTML page. The value NO (the default) enables the index and
+# the value YES disables it.
+
+DISABLE_INDEX = NO
+
+# This tag can be used to set the number of enum values (range [1..20])
+# that doxygen will group on one line in the generated HTML documentation.
+
+ENUM_VALUES_PER_LINE = 4
+
+# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be
+# generated containing a tree-like index structure (just like the one that
+# is generated for HTML Help). For this to work a browser that supports
+# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+,
+# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are
+# probably better off using the HTML help feature.
+
+GENERATE_TREEVIEW = YES
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
+# used to set the initial width (in pixels) of the frame in which the tree
+# is shown.
+
+TREEVIEW_WIDTH = 250
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
+# generate Latex output.
+
+GENERATE_LATEX = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked. If left blank `latex' will be used as the default command name.
+
+LATEX_CMD_NAME = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
+# generate index for LaTeX. If left blank `makeindex' will be used as the
+# default command name.
+
+MAKEINDEX_CMD_NAME = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
+# LaTeX documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_LATEX = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used
+# by the printer. Possible values are: a4, a4wide, letter, legal and
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE = a4wide
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
+# the generated latex document. The header should contain everything until
+# the first chapter. If it is left blank doxygen will generate a
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will
+# contain links (just like the HTML output) instead of page references
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS = YES
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
+# plain latex in the generated Makefile. Set this option to YES to get a
+# higher quality PDF documentation.
+
+USE_PDFLATEX = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
+# command to the generated LaTeX files. This will instruct LaTeX to keep
+# running if errors occur, instead of asking the user for help.
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE = YES
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not
+# include the index chapters (such as File Index, Compound Index, etc.)
+# in the output.
+
+LATEX_HIDE_INDICES = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
+# The RTF output is optimized for Word 97 and may not look very pretty with
+# other RTF readers or editors.
+
+GENERATE_RTF = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
+# RTF documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_RTF = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
+# will contain hyperlink fields. The RTF file will
+# contain links (just like the HTML output) instead of page references.
+# This makes the output suitable for online browsing using WORD or other
+# programs which support those fields.
+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's
+# config file, i.e. a series of assignments. You only have to provide
+# replacements, missing definitions are set to their default value.
+
+RTF_STYLESHEET_FILE =
+
+# Set optional variables used in the generation of an rtf document.
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
+# generate man pages
+
+GENERATE_MAN = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT = man
+
+# The MAN_EXTENSION tag determines the extension that is added to
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
+# then it will generate one additional man file for each entity
+# documented in the real man page(s). These additional files
+# only source the real man page, but without them the man command
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will
+# generate an XML file that captures the structure of
+# the code including all documentation.
+
+GENERATE_XML = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_SCHEMA =
+
+# The XML_DTD tag can be used to specify an XML DTD,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_DTD =
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
+# dump the program listings (including syntax highlighting
+# and cross-referencing information) to the XML output. Note that
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING = YES
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
+# generate an AutoGen Definitions (see autogen.sf.net) file
+# that captures the structure of the code including all
+# documentation. Note that this feature is still experimental
+# and incomplete at the moment.
+
+GENERATE_AUTOGEN_DEF = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will
+# generate a Perl module file that captures the structure of
+# the code including all documentation. Note that this
+# feature is still experimental and incomplete at the
+# moment.
+
+GENERATE_PERLMOD = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
+# nicely formatted so it can be parsed by a human reader. This is useful
+# if you want to understand what is going on. On the other hand, if this
+# tag is set to NO the size of the Perl module output will be much smaller
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY = YES
+
+# The names of the make variables in the generated doxyrules.make file
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
+# This is useful so different doxyrules.make files included by the same
+# Makefile don't overwrite each other's variables.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
+# evaluate all C-preprocessor directives found in the sources and include
+# files.
+
+ENABLE_PREPROCESSING = YES
+
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
+# names in the source code. If set to NO (the default) only conditional
+# compilation will be performed. Macro expansion can be done in a controlled
+# way by setting EXPAND_ONLY_PREDEF to YES.
+
+MACRO_EXPANSION = YES
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
+# then the macro expansion is limited to the macros specified with the
+# PREDEFINED and EXPAND_AS_PREDEFINED tags.
+
+EXPAND_ONLY_PREDEF = YES
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
+# in the INCLUDE_PATH (see below) will be search if a #include is found.
+
+SEARCH_INCLUDES = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by
+# the preprocessor.
+
+INCLUDE_PATH = ../include
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will
+# be used.
+
+INCLUDE_FILE_PATTERNS =
+
+# The PREDEFINED tag can be used to specify one or more macro names that
+# are defined before the preprocessor is started (similar to the -D option of
+# gcc). The argument of the tag is a list of macros of the form: name
+# or name=definition (no spaces). If the definition and the = are
+# omitted =1 is assumed.
+
+PREDEFINED =
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
+# this tag can be used to specify a list of macro names that should be expanded.
+# The macro definition that is found in the sources will be used.
+# Use the PREDEFINED tag if you want to use a different macro definition.
+
+EXPAND_AS_DEFINED =
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
+# doxygen's preprocessor will remove all function-like macros that are alone
+# on a line, have an all uppercase name, and do not end with a semicolon. Such
+# function macros are typically used for boiler-plate code, and will confuse the
+# parser if not removed.
+
+SKIP_FUNCTION_MACROS = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES option can be used to specify one or more tagfiles.
+# Optionally an initial location of the external documentation
+# can be added for each tagfile. The format of a tag file without
+# this location is as follows:
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where "loc1" and "loc2" can be relative or absolute paths or
+# URLs. If a location is present for each tag, the installdox tool
+# does not have to be run to correct the links.
+# Note that each tag file must have a unique name
+# (where the name does NOT include the path)
+# If a tag file is not located in the directory in which doxygen
+# is run, you must also specify the path to the tagfile here.
+
+TAGFILES =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create
+# a tag file that is based on the input files it reads.
+
+GENERATE_TAGFILE =
+
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed
+# in the class index. If set to NO only the inherited external classes
+# will be listed.
+
+ALLEXTERNALS = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will
+# be listed.
+
+EXTERNAL_GROUPS = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of `which perl').
+
+PERL_PATH = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base or
+# super classes. Setting the tag to NO turns the diagrams off. Note that this
+# option is superseded by the HAVE_DOT option below. This is only a fallback. It is
+# recommended to install and use dot, since it yields more powerful graphs.
+
+CLASS_DIAGRAMS = YES
+
+# If set to YES, the inheritance and collaboration graphs will hide
+# inheritance and usage relations if the target is undocumented
+# or is not a class.
+
+HIDE_UNDOC_RELATIONS = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz, a graph visualization
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section
+# have no effect if this option is set to NO (the default)
+
+HAVE_DOT = YES
+
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect inheritance relations. Setting this tag to YES will force the
+# the CLASS_DIAGRAMS tag to NO.
+
+CLASS_GRAPH = YES
+
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect implementation dependencies (inheritance, containment, and
+# class references variables) of the class with other documented classes.
+
+COLLABORATION_GRAPH = YES
+
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+
+UML_LOOK = NO
+
+# If set to YES, the inheritance and collaboration graphs will show the
+# relations between templates and their instances.
+
+TEMPLATE_RELATIONS = NO
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
+# tags are set to YES then doxygen will generate a graph for each documented
+# file showing the direct and indirect include dependencies of the file with
+# other documented files.
+
+INCLUDE_GRAPH = YES
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
+# documented header file showing the documented files that directly or
+# indirectly include this file.
+
+INCLUDED_BY_GRAPH = YES
+
+# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will
+# generate a call dependency graph for every global function or class method.
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable call graphs for selected
+# functions only using the \callgraph command.
+
+CALL_GRAPH = NO
+
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
+# will graphical hierarchy of all classes instead of a textual one.
+
+GRAPHICAL_HIERARCHY = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. Possible values are png, jpg, or gif
+# If left blank png will be used.
+
+DOT_IMAGE_FORMAT = png
+
+# The tag DOT_PATH can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found on the path.
+
+DOT_PATH =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the
+# \dotfile command).
+
+DOTFILE_DIRS =
+
+# The MAX_DOT_GRAPH_WIDTH tag can be used to set the maximum allowed width
+# (in pixels) of the graphs generated by dot. If a graph becomes larger than
+# this value, doxygen will try to truncate the graph, so that it fits within
+# the specified constraint. Beware that most browsers cannot cope with very
+# large images.
+
+MAX_DOT_GRAPH_WIDTH = 1024
+
+# The MAX_DOT_GRAPH_HEIGHT tag can be used to set the maximum allows height
+# (in pixels) of the graphs generated by dot. If a graph becomes larger than
+# this value, doxygen will try to truncate the graph, so that it fits within
+# the specified constraint. Beware that most browsers cannot cope with very
+# large images.
+
+MAX_DOT_GRAPH_HEIGHT = 1024
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
+# graphs generated by dot. A depth value of 3 means that only nodes reachable
+# from the root by following a path via at most 3 edges will be shown. Nodes that
+# lay further from the root node will be omitted. Note that setting this option to
+# 1 or 2 may greatly reduce the computation time needed for large code bases. Also
+# note that a graph may be further truncated if the graph's image dimensions are
+# not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH and MAX_DOT_GRAPH_HEIGHT).
+# If 0 is used for the depth value (the default), the graph is not depth-constrained.
+
+MAX_DOT_GRAPH_DEPTH = 0
+
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
+# generate a legend page explaining the meaning of the various boxes and
+# arrows in the dot generated graphs.
+
+GENERATE_LEGEND = YES
+
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
+# remove the intermediate dot files that are used to generate
+# the various graphs.
+
+DOT_CLEANUP = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+
+# The SEARCHENGINE tag specifies whether or not a search engine should be
+# used. If set to NO the values of all tags below this one will be ignored.
+
+SEARCHENGINE = YES
GEDA_PATH=/usr/share/gEDA/scheme
FILES=aicpic.sch aicpower.sch
-all: pdf drc bom partslist net
+all: pdf drc bom partslist net html
drc: aic.drc
#aic_pin_silk.ps: aic_frontsilk.ps aic_front.ps
# MergePCBPS aic_frontsilk.ps aic_front.ps > aic_pin_silk.ps
+html: html/index.html
+
+html/index.html: Doxyfile
+ doxygen
+
+
clean:
rm -rf *.log *~ tmp.ps aicpic.ps aicpower.ps *.bak* aic_pin_silk.ps *.eps aic.pcb- *.old
rm -rf *.drc *.bom *.bpp *.xrf *.csv *.pl1 *.pl2 *.pl3 *.net aic.pdf *.tgz
distclean: mrproper
- rm -rf aicpic.ps aicpower.ps
+ rm -rf aicpic.ps aicpower.ps html
value=47uFx16V
T 3000 78800 5 10 0 0 0 0 1
footprint=RCY100P
-T 3000 78800 5 10 1 1 0 0 1
+T 3000 78800 5 10 0 1 0 0 1
symversion=0.100
}
C 5000 77900 1 90 0 capacitor-1.sym
value=100nF
T 5000 77900 5 10 0 0 0 0 1
footprint=RCI200
-T 5000 77900 5 10 1 1 0 0 1
+T 5000 77900 5 10 0 1 0 0 1
symversion=0.100
}
C 10200 79000 1 180 0 resistor-1.sym
value=47uFx16V
T 7300 78800 5 10 0 0 0 0 1
footprint=RCY100P
-T 7300 78800 5 10 1 1 0 0 1
+T 7300 78800 5 10 0 1 0 0 1
symversion=0.100
}
C 8700 77900 1 90 0 capacitor-1.sym
value=100nF
T 8700 77900 5 10 0 0 0 0 1
footprint=RCI200
-T 8700 77900 5 10 1 1 0 0 1
+T 8700 77900 5 10 0 1 0 0 1
symversion=0.100
}
C 8400 77000 1 0 0 gnd-1.sym
value=2.2nF
T 4500 77900 5 10 0 0 0 0 1
footprint=RCI200
-T 4500 77900 5 10 1 1 0 0 1
+T 4500 77900 5 10 0 1 0 0 1
symversion=0.100
}
N 3600 77700 3200 77700 4
value=100nF
T 4400 74700 5 10 0 0 0 0 1
footprint=RCI200
-T 4400 74700 5 10 1 1 0 0 1
+T 4400 74700 5 10 0 1 0 0 1
symversion=0.100
}
C 5500 74700 1 90 0 capacitor-1.sym
value=100nF
T 5500 74700 5 10 0 0 0 0 1
footprint=RCI200
-T 5500 74700 5 10 1 1 0 0 1
+T 5500 74700 5 10 0 1 0 0 1
symversion=0.100
}
C 4000 75600 1 0 0 5V-plus-1.sym
footprint=RCY100P
T 8200 83800 5 10 1 1 0 0 1
value=1uFx16V
-T 9100 84400 5 10 1 1 0 0 1
+T 9100 84400 5 10 0 1 0 0 1
symversion=0.100
}
C 5300 84000 1 0 0 capacitor-4.sym
footprint=RCY100P
T 4700 84200 5 10 1 1 0 0 1
value=1uFx16V
-T 5300 84000 5 10 1 1 0 0 1
+T 5300 84000 5 10 0 1 0 0 1
symversion=0.100
}
C 5300 83200 1 0 0 capacitor-4.sym
footprint=RCY100P
T 4700 83400 5 10 1 1 0 0 1
value=1uFx16V
-T 5300 83200 5 10 1 1 0 0 1
+T 5300 83200 5 10 0 1 0 0 1
symversion=0.100
}
C 8200 83200 1 0 0 capacitor-4.sym
footprint=RCY100P
T 8200 83000 5 10 1 1 0 0 1
value=1uFx16V
-T 8200 83200 5 10 1 1 0 0 1
+T 8200 83200 5 10 0 1 0 0 1
symversion=0.100
}
C 7300 79400 1 0 0 vcc-1.sym
value=100nF
T 7600 74700 5 10 0 0 0 0 1
footprint=RCI200
-T 7600 74700 5 10 1 1 0 0 1
+T 7600 74700 5 10 0 1 0 0 1
symversion=0.100
}
C 8600 74700 1 90 0 capacitor-1.sym
value=100nF
T 8600 74700 5 10 0 0 0 0 1
footprint=RCI200
-T 8600 74700 5 10 1 1 0 0 1
+T 8600 74700 5 10 0 1 0 0 1
symversion=0.100
}
C 8100 75600 1 0 1 generic-power.sym
value=1uFx16V
T 3000 75600 5 10 0 1 0 0 1
footprint=RCY100P
-T 3000 75600 5 10 1 1 0 0 1
+T 3000 75600 5 10 0 1 0 0 1
symversion=0.100
}
C 7600 87200 1 180 0 capacitor-4.sym
value=1uFx16V
T 7600 87200 5 10 0 1 270 0 1
footprint=RCY100P
-T 7600 87200 5 10 1 1 0 0 1
+T 7600 87200 5 10 0 1 0 0 1
symversion=0.100
}
N 18900 84000 22100 84000 4
refdes=C26
T 18900 85600 5 10 1 1 0 0 1
value=2.2nF
-T 19600 85400 5 10 1 1 0 0 1
+T 19600 85400 5 10 0 1 0 0 1
symversion=0.100
}
C 20400 85400 1 90 0 capacitor-1.sym
refdes=C27
T 19700 85600 5 10 1 1 0 0 1
value=2.2nF
-T 20400 85400 5 10 1 1 0 0 1
+T 20400 85400 5 10 0 1 0 0 1
symversion=0.100
}
N 19400 86900 19400 86300 4
T 17300 73900 9 10 1 0 0 0 1
aicpower.sch
T 21200 73900 9 10 1 0 0 0 1
-2.1.0
+2.2.0
T 22200 73700 9 6 1 0 0 0 2
Walter Fetter Lages
Diego Caberlon Santini
footprint=RCY100P
T 11400 79400 5 10 1 1 0 0 1
value=4.7uFx16V
-T 11100 80100 5 10 1 1 0 0 1
+T 11100 80100 5 10 0 1 0 0 1
symversion=0.100
}
N 9600 80100 11300 80100 4
value=100nF
T 10400 79200 5 10 0 0 0 0 1
footprint=RCI200
-T 10400 79200 5 10 1 1 0 0 1
+T 10400 79200 5 10 0 1 0 0 1
symversion=0.100
}
C 14300 78400 1 0 0 output-2.sym
footprint=RCY300P
T 8400 86400 5 10 1 1 0 0 1
value=1000uFx100V
-T 8400 87200 5 10 1 1 0 0 1
+T 8400 87200 5 10 0 1 0 0 1
symversion=0.100
}
N 8200 87200 8600 87200 4
footprint=RCY100P
T 1300 86600 5 10 1 1 0 0 1
value=10uFx16V
-T 2100 87300 5 10 1 1 0 0 1
+T 2100 87300 5 10 0 1 0 0 1
symversion=0.100
}
C 2200 86100 1 0 0 gnd-1.sym
value=100nF
T 2900 86400 5 10 0 0 0 0 1
footprint=RCI200
-T 3000 86400 5 10 1 1 0 0 1
+T 3000 86400 5 10 0 1 0 0 1
symversion=0.100
}
C 7700 85200 1 0 0 IRLZ24N-1.sym
footprint=RCY100P
T 16200 86400 5 10 1 1 0 0 1
value=10uFx16V
-T 16600 87300 5 10 1 1 0 0 1
+T 16600 87300 5 10 0 1 0 0 1
symversion=0.100
}
C 16900 86100 1 0 1 gnd-1.sym
value=100nF
T 16300 86400 5 10 0 0 0 0 1
footprint=RCI200
-T 16300 86400 5 10 1 1 0 0 1
+T 16300 86400 5 10 0 1 0 0 1
symversion=0.100
}
N 11000 86000 11000 87200 4
footprint=RCY100P
T 6700 85200 5 10 1 1 0 6 1
value=1uFx16V
-T 6500 86000 5 10 1 1 0 0 1
+T 6500 86000 5 10 0 1 0 0 1
symversion=0.100
}
C 5100 87100 1 0 0 diode-1.sym
footprint=RCY100P
T 12600 85200 5 10 1 1 0 0 1
value=1uFx16V
-T 12700 86000 5 10 1 1 0 0 1
+T 12700 86000 5 10 0 1 0 0 1
symversion=0.100
}
N 13200 84200 12400 84200 4
--- /dev/null
+cross-pic30-elf-binutils-2.14.mplab.3.01-1mdk.i586.tgz
+
+cross-pic30-elf-gcc-4.0.mplab.3.01-1mdk.i586.tgz
+
+MPLABC30v2_00Full.exe
+mplabc30v2_00_serial.txt
+
+FreeRTOSV4.7.2.zip
+<http://www.freertos.org>
+<http://sourceforge.net/projects/freertos>
\ No newline at end of file
+++ /dev/null
-/*\r
-** Linker Script for 30f4012\r
-*/\r
-\r
-OUTPUT_ARCH("30f4012")\r
-EXTERN(__resetPRI)\r
-EXTERN(__resetALT)\r
-\r
-\r
-/*\r
-** Memory Regions\r
-*/\r
-MEMORY\r
-{\r
- data (a!xr) : ORIGIN = 0x800, LENGTH = 2048\r
- program (xr) : ORIGIN = 0x100, LENGTH = ((16K * 2) - 0x100)\r
- reset : ORIGIN = 0, LENGTH = (4)\r
- ivt : ORIGIN = 0x04, LENGTH = (62 * 2)\r
- aivt : ORIGIN = 0x84, LENGTH = (62 * 2)\r
- __FOSC : ORIGIN = 0xF80000, LENGTH = (2)\r
- __FWDT : ORIGIN = 0xF80002, LENGTH = (2)\r
- __FBORPOR : ORIGIN = 0xF80004, LENGTH = (2)\r
- __CONFIG4 : ORIGIN = 0xF80006, LENGTH = (2)\r
- __CONFIG5 : ORIGIN = 0xF80008, LENGTH = (2)\r
- __FGS : ORIGIN = 0xF8000A, LENGTH = (2)\r
- eedata : ORIGIN = 0x7FFC00, LENGTH = (1024)\r
-}\r
-__NO_HANDLES = 1; /* Suppress handles on this device */\r
-\r
-\r
-/*\r
-** Base Memory Addresses - Program Memory\r
-*/\r
-__RESET_BASE = 0; /* Reset Instruction */\r
-__IVT_BASE = 0x04; /* Interrupt Vector Table */\r
-__AIVT_BASE = 0x84; /* Alternate Interrupt Vector Table */\r
-__CODE_BASE = 0x100; /* Handles, User Code, Library Code */\r
-\r
-\r
-/*\r
-** Base Memory Addresses - Data Memory\r
-*/\r
-__SFR_BASE = 0; /* Memory-mapped SFRs */\r
-__DATA_BASE = 0x800; /* X and General Purpose Data Memory */\r
-__YDATA_BASE = 0x0C00; /* Y Data Memory for DSP Instructions */\r
-\r
-\r
-/*\r
-** ==================== Section Map ======================\r
-*/\r
-\r
-SECTIONS\r
-{\r
-\r
- /*\r
- ** ================== Program Memory =====================\r
- */\r
-\r
- /*\r
- ** Reset Instruction\r
- */\r
- .reset __RESET_BASE :\r
- {\r
- SHORT(ABSOLUTE(__reset));\r
- SHORT(0x04);\r
- SHORT((ABSOLUTE(__reset) >> 16) & 0x7F);\r
- SHORT(0);\r
- } >reset\r
-\r
-\r
- /*\r
- ** Interrupt Vector Tables\r
- **\r
- ** The primary and alternate tables are loaded\r
- ** here, between sections .reset and .text.\r
- ** Vector table source code appears below.\r
- */\r
-\r
- /*\r
- ** User Code and Library Code\r
- */\r
- .text __CODE_BASE :\r
- {\r
- *(.handle);\r
- *(.libc) *(.libm) *(.libdsp); /* keep together in this order */\r
- *(.lib*);\r
- *(.text);\r
- } >program\r
-\r
- /*\r
- ** User-Defined Section in Program Memory\r
- **\r
- ** note: can specify an address using\r
- ** the following syntax:\r
- **\r
- ** usercode 0x1234 :\r
- ** {\r
- ** *(usercode);\r
- ** } >program\r
- */\r
- usercode :\r
- {\r
- *(usercode);\r
- } >program\r
-\r
-\r
- /*\r
- ** ================ Configuration Memory ================\r
- */\r
-\r
-\r
- /*\r
- ** Configuration Fuses\r
- */\r
- __FOSC :\r
- { *(__FOSC.sec) } >__FOSC\r
- __FWDT :\r
- { *(__FWDT.sec) } >__FWDT\r
- __FBORPOR :\r
- { *(__FBORPOR.sec) } >__FBORPOR\r
- __CONFIG4 :\r
- { *(__CONFIG4.sec) } >__CONFIG4\r
- __CONFIG5 :\r
- { *(__CONFIG5.sec) } >__CONFIG5\r
- __FGS :\r
- { *(__FGS.sec) } >__FGS\r
-\r
-\r
- /*\r
- ** User-Defined Section in Data Flash Memory\r
- **\r
- ** note: can specify an address using\r
- ** the following syntax:\r
- **\r
- ** user_eedata 0x7FFC00 :\r
- ** {\r
- ** *(user_eedata);\r
- ** } >eedata\r
- */\r
- user_eedata :\r
- {\r
- *(user_eedata);\r
- } >eedata\r
-\r
-\r
- /*\r
- ** ==================== Data Memory ===================\r
- */\r
-\r
- /* \r
- ** ICD Debug Exec\r
- **\r
- ** This section provides optional storage for\r
- ** the ICD2 debugger. Define a global symbol\r
- ** named __ICD2RAM to enable ICD2. This section\r
- ** must be loaded at data address 0x800.\r
- */ \r
- .icd __DATA_BASE (NOLOAD): \r
- { \r
- . += (DEFINED (__ICD2RAM) ? 0x50 : 0 ); \r
- } > data \r
-\r
-\r
- /*\r
- ** User-Defined Section in Data Memory\r
- **\r
- ** note: can specify an address using\r
- ** the following syntax:\r
- **\r
- ** userdata 0x1234 :\r
- ** {\r
- ** *(userdata);\r
- ** } >data\r
- */\r
- userdata :\r
- {\r
- *(userdata);\r
- } >data\r
-\r
-\r
- /*\r
- ** ===================== Debug Info ====================\r
- */\r
-\r
- .comment 0 : { *(.comment) }\r
-\r
- /*\r
- ** DWARF-2\r
- */\r
- .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }\r
- .debug_abbrev 0 : { *(.debug_abbrev) }\r
- .debug_line 0 : { *(.debug_line) }\r
- .debug_frame 0 : { *(.debug_frame) }\r
- .debug_str 0 : { *(.debug_str) }\r
- .debug_loc 0 : { *(.debug_loc) }\r
- .debug_macinfo 0 : { *(.debug_macinfo) }\r
- .debug_pubnames 0 : { *(.debug_pubnames) }\r
- .debug_ranges 0 : { *(.debug_ranges) }\r
- .debug_aranges 0 : { *(.debug_aranges) }\r
-\r
-} /* SECTIONS */\r
-\r
-/*\r
-** ================= End of Section Map ================\r
-*/\r
-/*\r
-** Section Map for Interrupt Vector Tables\r
-*/\r
-SECTIONS\r
-{\r
-\r
-/*\r
-** Primary Interrupt Vector Table\r
-*/\r
-.ivt __IVT_BASE :\r
- {\r
- LONG(DEFINED(__ReservedTrap0\r
-) ? ABSOLUTE(__ReservedTrap0\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__OscillatorFail\r
-)? ABSOLUTE(__OscillatorFail\r
-):\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__AddressError\r
-) ? ABSOLUTE(__AddressError\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__StackError\r
-) ? ABSOLUTE(__StackError\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__MathError\r
-) ? ABSOLUTE(__MathError\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__ReservedTrap5\r
-) ? ABSOLUTE(__ReservedTrap5\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__ReservedTrap6\r
-) ? ABSOLUTE(__ReservedTrap6\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__ReservedTrap7\r
-) ? ABSOLUTE(__ReservedTrap7\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__INT0Interrupt\r
-) ? ABSOLUTE(__INT0Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__IC1Interrupt\r
-) ? ABSOLUTE(__IC1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__OC1Interrupt\r
-) ? ABSOLUTE(__OC1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__T1Interrupt\r
-) ? ABSOLUTE(__T1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__IC2Interrupt\r
-) ? ABSOLUTE(__IC2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__OC2Interrupt\r
-) ? ABSOLUTE(__OC2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__T2Interrupt\r
-) ? ABSOLUTE(__T2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__T3Interrupt\r
-) ? ABSOLUTE(__T3Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__SPI1Interrupt\r
-) ? ABSOLUTE(__SPI1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__U1RXInterrupt\r
-) ? ABSOLUTE(__U1RXInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__U1TXInterrupt\r
-) ? ABSOLUTE(__U1TXInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__ADCInterrupt\r
-) ? ABSOLUTE(__ADCInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__NVMInterrupt\r
-) ? ABSOLUTE(__NVMInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__SI2CInterrupt\r
-) ? ABSOLUTE(__SI2CInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__MI2CInterrupt\r
-) ? ABSOLUTE(__MI2CInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__CNInterrupt\r
-) ? ABSOLUTE(__CNInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__INT1Interrupt\r
-) ? ABSOLUTE(__INT1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__IC7Interrupt\r
-) ? ABSOLUTE(__IC7Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__IC8Interrupt\r
-) ? ABSOLUTE(__IC8Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__OC3Interrupt\r
-) ? ABSOLUTE(__OC3Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__OC4Interrupt\r
-) ? ABSOLUTE(__OC4Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__T4Interrupt\r
-) ? ABSOLUTE(__T4Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__T5Interrupt\r
-) ? ABSOLUTE(__T5Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__INT2Interrupt\r
-) ? ABSOLUTE(__INT2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__U2RXInterrupt\r
-) ? ABSOLUTE(__U2RXInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__U2TXInterrupt\r
-) ? ABSOLUTE(__U2TXInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__SPI2Interrupt\r
-) ? ABSOLUTE(__SPI2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__C1Interrupt\r
-) ? ABSOLUTE(__C1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__IC3Interrupt\r
-) ? ABSOLUTE(__IC3Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__IC4Interrupt\r
-) ? ABSOLUTE(__IC4Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__IC5Interrupt\r
-) ? ABSOLUTE(__IC5Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__IC6Interrupt\r
-) ? ABSOLUTE(__IC6Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__OC5Interrupt\r
-) ? ABSOLUTE(__OC5Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__OC6Interrupt\r
-) ? ABSOLUTE(__OC6Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__OC7Interrupt\r
-) ? ABSOLUTE(__OC7Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__OC8Interrupt\r
-) ? ABSOLUTE(__OC8Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__INT3Interrupt\r
-) ? ABSOLUTE(__INT3Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__INT4Interrupt\r
-) ? ABSOLUTE(__INT4Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__C2Interrupt\r
-) ? ABSOLUTE(__C2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__PWMInterrupt\r
-) ? ABSOLUTE(__PWMInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__QEIInterrupt\r
-) ? ABSOLUTE(__QEIInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__DCIInterrupt\r
-) ? ABSOLUTE(__DCIInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__LVDInterrupt\r
-) ? ABSOLUTE(__LVDInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__FLTAInterrupt\r
-) ? ABSOLUTE(__FLTAInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__FLTBInterrupt\r
-) ? ABSOLUTE(__FLTBInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__Interrupt45\r
-) ? ABSOLUTE(__Interrupt45\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__Interrupt46\r
-) ? ABSOLUTE(__Interrupt46\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__Interrupt47\r
-) ? ABSOLUTE(__Interrupt47\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__Interrupt48\r
-) ? ABSOLUTE(__Interrupt48\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__Interrupt49\r
-) ? ABSOLUTE(__Interrupt49\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__Interrupt50\r
-) ? ABSOLUTE(__Interrupt50\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__Interrupt51\r
-) ? ABSOLUTE(__Interrupt51\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__Interrupt52\r
-) ? ABSOLUTE(__Interrupt52\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- LONG(DEFINED(__Interrupt53\r
-) ? ABSOLUTE(__Interrupt53\r
-) :\r
- ABSOLUTE(__DefaultInterrupt));\r
- } >ivt\r
-\r
-\r
-/*\r
-** Alternate Interrupt Vector Table\r
-*/\r
-.aivt __AIVT_BASE :\r
- {\r
- LONG(DEFINED(__AltReservedTrap0\r
-) ? ABSOLUTE(__AltReservedTrap0\r
-) :\r
- (DEFINED(__ReservedTrap0\r
-) ? ABSOLUTE(__ReservedTrap0\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltOscillatorFail\r
-)? ABSOLUTE(__AltOscillatorFail\r
-):\r
- (DEFINED(__OscillatorFail\r
-) ? ABSOLUTE(__OscillatorFail\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltAddressError\r
-) ? ABSOLUTE(__AltAddressError\r
-) :\r
- (DEFINED(__AddressError\r
-) ? ABSOLUTE(__AddressError\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltStackError\r
-) ? ABSOLUTE(__AltStackError\r
-) :\r
- (DEFINED(__StackError\r
-) ? ABSOLUTE(__StackError\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltMathError\r
-) ? ABSOLUTE(__AltMathError\r
-) :\r
- (DEFINED(__MathError\r
-) ? ABSOLUTE(__MathError\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltReservedTrap5\r
-) ? ABSOLUTE(__AltReservedTrap5\r
-) :\r
- (DEFINED(__ReservedTrap5\r
-) ? ABSOLUTE(__ReservedTrap5\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltReservedTrap6\r
-) ? ABSOLUTE(__AltReservedTrap6\r
-) :\r
- (DEFINED(__ReservedTrap6\r
-) ? ABSOLUTE(__ReservedTrap6\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltReservedTrap7\r
-) ? ABSOLUTE(__AltReservedTrap7\r
-) :\r
- (DEFINED(__ReservedTrap7\r
-) ? ABSOLUTE(__ReservedTrap7\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltINT0Interrupt\r
-) ? ABSOLUTE(__AltINT0Interrupt\r
-) :\r
- (DEFINED(__INT0Interrupt\r
-) ? ABSOLUTE(__INT0Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltIC1Interrupt\r
-) ? ABSOLUTE(__AltIC1Interrupt\r
-) :\r
- (DEFINED(__IC1Interrupt\r
-) ? ABSOLUTE(__IC1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltOC1Interrupt\r
-) ? ABSOLUTE(__AltOC1Interrupt\r
-) :\r
- (DEFINED(__OC1Interrupt\r
-) ? ABSOLUTE(__OC1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltT1Interrupt\r
-) ? ABSOLUTE(__AltT1Interrupt\r
-) :\r
- (DEFINED(__T1Interrupt\r
-) ? ABSOLUTE(__T1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltIC2Interrupt\r
-) ? ABSOLUTE(__AltIC2Interrupt\r
-) :\r
- (DEFINED(__IC2Interrupt\r
-) ? ABSOLUTE(__IC2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltOC2Interrupt\r
-) ? ABSOLUTE(__AltOC2Interrupt\r
-) :\r
- (DEFINED(__OC2Interrupt\r
-) ? ABSOLUTE(__OC2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltT2Interrupt\r
-) ? ABSOLUTE(__AltT2Interrupt\r
-) :\r
- (DEFINED(__T2Interrupt\r
-) ? ABSOLUTE(__T2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltT3Interrupt\r
-) ? ABSOLUTE(__AltT3Interrupt\r
-) :\r
- (DEFINED(__T3Interrupt\r
-) ? ABSOLUTE(__T3Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltSPI1Interrupt\r
-) ? ABSOLUTE(__AltSPI1Interrupt\r
-) :\r
- (DEFINED(__SPI1Interrupt\r
-) ? ABSOLUTE(__SPI1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltU1RXInterrupt\r
-) ? ABSOLUTE(__AltU1RXInterrupt\r
-) :\r
- (DEFINED(__U1RXInterrupt\r
-) ? ABSOLUTE(__U1RXInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltU1TXInterrupt\r
-) ? ABSOLUTE(__AltU1TXInterrupt\r
-) :\r
- (DEFINED(__U1TXInterrupt\r
-) ? ABSOLUTE(__U1TXInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltADCInterrupt\r
-) ? ABSOLUTE(__AltADCInterrupt\r
-) :\r
- (DEFINED(__ADCInterrupt\r
-) ? ABSOLUTE(__ADCInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltNVMInterrupt\r
-) ? ABSOLUTE(__AltNVMInterrupt\r
-) :\r
- (DEFINED(__NVMInterrupt\r
-) ? ABSOLUTE(__NVMInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltSI2CInterrupt\r
-) ? ABSOLUTE(__AltSI2CInterrupt\r
-) :\r
- (DEFINED(__SI2CInterrupt\r
-) ? ABSOLUTE(__SI2CInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltMI2CInterrupt\r
-) ? ABSOLUTE(__AltMI2CInterrupt\r
-) :\r
- (DEFINED(__MI2CInterrupt\r
-) ? ABSOLUTE(__MI2CInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltCNInterrupt\r
-) ? ABSOLUTE(__AltCNInterrupt\r
-) :\r
- (DEFINED(__CNInterrupt\r
-) ? ABSOLUTE(__CNInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltINT1Interrupt\r
-) ? ABSOLUTE(__AltINT1Interrupt\r
-) :\r
- (DEFINED(__INT1Interrupt\r
-) ? ABSOLUTE(__INT1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltIC7Interrupt\r
-) ? ABSOLUTE(__AltIC7Interrupt\r
-) :\r
- (DEFINED(__IC7Interrupt\r
-) ? ABSOLUTE(__IC7Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltIC8Interrupt\r
-) ? ABSOLUTE(__AltIC8Interrupt\r
-) :\r
- (DEFINED(__IC8Interrupt\r
-) ? ABSOLUTE(__IC8Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltOC3Interrupt\r
-) ? ABSOLUTE(__AltOC3Interrupt\r
-) :\r
- (DEFINED(__OC3Interrupt\r
-) ? ABSOLUTE(__OC3Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltOC4Interrupt\r
-) ? ABSOLUTE(__AltOC4Interrupt\r
-) :\r
- (DEFINED(__OC4Interrupt\r
-) ? ABSOLUTE(__OC4Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltT4Interrupt\r
-) ? ABSOLUTE(__AltT4Interrupt\r
-) :\r
- (DEFINED(__T4Interrupt\r
-) ? ABSOLUTE(__T4Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltT5Interrupt\r
-) ? ABSOLUTE(__AltT5Interrupt\r
-) :\r
- (DEFINED(__T5Interrupt\r
-) ? ABSOLUTE(__T5Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltINT2Interrupt\r
-) ? ABSOLUTE(__AltINT2Interrupt\r
-) :\r
- (DEFINED(__INT2Interrupt\r
-) ? ABSOLUTE(__INT2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltU2RXInterrupt\r
-) ? ABSOLUTE(__AltU2RXInterrupt\r
-) :\r
- (DEFINED(__U2RXInterrupt\r
-) ? ABSOLUTE(__U2RXInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltU2TXInterrupt\r
-) ? ABSOLUTE(__AltU2TXInterrupt\r
-) :\r
- (DEFINED(__U2TXInterrupt\r
-) ? ABSOLUTE(__U2TXInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltSPI2Interrupt\r
-) ? ABSOLUTE(__AltSPI2Interrupt\r
-) :\r
- (DEFINED(__SPI2Interrupt\r
-) ? ABSOLUTE(__SPI2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltC1Interrupt\r
-) ? ABSOLUTE(__AltC1Interrupt\r
-) :\r
- (DEFINED(__C1Interrupt\r
-) ? ABSOLUTE(__C1Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltIC3Interrupt\r
-) ? ABSOLUTE(__AltIC3Interrupt\r
-) :\r
- (DEFINED(__IC3Interrupt\r
-) ? ABSOLUTE(__IC3Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltIC4Interrupt\r
-) ? ABSOLUTE(__AltIC4Interrupt\r
-) :\r
- (DEFINED(__IC4Interrupt\r
-) ? ABSOLUTE(__IC4Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltIC5Interrupt\r
-) ? ABSOLUTE(__AltIC5Interrupt\r
-) :\r
- (DEFINED(__IC5Interrupt\r
-) ? ABSOLUTE(__IC5Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltIC6Interrupt\r
-) ? ABSOLUTE(__AltIC6Interrupt\r
-) :\r
- (DEFINED(__IC6Interrupt\r
-) ? ABSOLUTE(__IC6Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltOC5Interrupt\r
-) ? ABSOLUTE(__AltOC5Interrupt\r
-) :\r
- (DEFINED(__OC5Interrupt\r
-) ? ABSOLUTE(__OC5Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltOC6Interrupt\r
-) ? ABSOLUTE(__AltOC6Interrupt\r
-) :\r
- (DEFINED(__OC6Interrupt\r
-) ? ABSOLUTE(__OC6Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltOC7Interrupt\r
-) ? ABSOLUTE(__AltOC7Interrupt\r
-) :\r
- (DEFINED(__OC7Interrupt\r
-) ? ABSOLUTE(__OC7Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltOC8Interrupt\r
-) ? ABSOLUTE(__AltOC8Interrupt\r
-) :\r
- (DEFINED(__OC8Interrupt\r
-) ? ABSOLUTE(__OC8Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltINT3Interrupt\r
-) ? ABSOLUTE(__AltINT3Interrupt\r
-) :\r
- (DEFINED(__INT3Interrupt\r
-) ? ABSOLUTE(__INT3Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltINT4Interrupt\r
-) ? ABSOLUTE(__AltINT4Interrupt\r
-) :\r
- (DEFINED(__INT4Interrupt\r
-) ? ABSOLUTE(__INT4Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltC2Interrupt\r
-) ? ABSOLUTE(__AltC2Interrupt\r
-) :\r
- (DEFINED(__C2Interrupt\r
-) ? ABSOLUTE(__C2Interrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltPWMInterrupt\r
-) ? ABSOLUTE(__AltPWMInterrupt\r
-) :\r
- (DEFINED(__PWMInterrupt\r
-) ? ABSOLUTE(__PWMInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltQEIInterrupt\r
-) ? ABSOLUTE(__AltQEIInterrupt\r
-) :\r
- (DEFINED(__QEIInterrupt\r
-) ? ABSOLUTE(__QEIInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltDCIInterrupt\r
-) ? ABSOLUTE(__AltDCIInterrupt\r
-) :\r
- (DEFINED(__DCIInterrupt\r
-) ? ABSOLUTE(__DCIInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltLVDInterrupt\r
-) ? ABSOLUTE(__AltLVDInterrupt\r
-) :\r
- (DEFINED(__LVDInterrupt\r
-) ? ABSOLUTE(__LVDInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltFLTAInterrupt\r
-) ? ABSOLUTE(__AltFLTAInterrupt\r
-) :\r
- (DEFINED(__FLTAInterrupt\r
-) ? ABSOLUTE(__FLTAInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltFLTBInterrupt\r
-) ? ABSOLUTE(__AltFLTBInterrupt\r
-) :\r
- (DEFINED(__FLTBInterrupt\r
-) ? ABSOLUTE(__FLTBInterrupt\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltInterrupt45\r
-) ? ABSOLUTE(__AltInterrupt45\r
-) :\r
- (DEFINED(__Interrupt45\r
-) ? ABSOLUTE(__Interrupt45\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltInterrupt46\r
-) ? ABSOLUTE(__AltInterrupt46\r
-) :\r
- (DEFINED(__Interrupt46\r
-) ? ABSOLUTE(__Interrupt46\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltInterrupt47\r
-) ? ABSOLUTE(__AltInterrupt47\r
-) :\r
- (DEFINED(__Interrupt47\r
-) ? ABSOLUTE(__Interrupt47\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltInterrupt48\r
-) ? ABSOLUTE(__AltInterrupt48\r
-) :\r
- (DEFINED(__Interrupt48\r
-) ? ABSOLUTE(__Interrupt48\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltInterrupt49\r
-) ? ABSOLUTE(__AltInterrupt49\r
-) :\r
- (DEFINED(__Interrupt49\r
-) ? ABSOLUTE(__Interrupt49\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltInterrupt50\r
-) ? ABSOLUTE(__AltInterrupt50\r
-) :\r
- (DEFINED(__Interrupt50\r
-) ? ABSOLUTE(__Interrupt50\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltInterrupt51\r
-) ? ABSOLUTE(__AltInterrupt51\r
-) :\r
- (DEFINED(__Interrupt51\r
-) ? ABSOLUTE(__Interrupt51\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltInterrupt52\r
-) ? ABSOLUTE(__AltInterrupt52\r
-) :\r
- (DEFINED(__Interrupt52\r
-) ? ABSOLUTE(__Interrupt52\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- LONG(DEFINED(__AltInterrupt53\r
-) ? ABSOLUTE(__AltInterrupt53\r
-) :\r
- (DEFINED(__Interrupt53\r
-) ? ABSOLUTE(__Interrupt53\r
-) :\r
- ABSOLUTE(__DefaultInterrupt)));\r
- } >aivt\r
-\r
-} /* SECTIONS */\r
-\r
-\r
-/* File Description | Notes:\r
-** =========================\r
-** 1] This file maps special function register(SFR) names used in the datasheet\r
-** to memory locations in the PIC30Fxxxx device. The memory locations are\r
-** byte addresses. The PIC30Fxxxx is a family of byte addressable devices.\r
-** 2] The register names used in this file are taken to match the\r
-** PIC30Fxxxx data sheets as closely as possible.\r
-** 3] SFR address definitions are listed in the ascending order of memory\r
-** addresses and are grouped based on the module they belong to. For e.g.,\r
-** WREG10 is listed before ACCAL, and the Core SFRs are grouped\r
-** separately, prior to the Interrupt Controller SFRs or the General\r
-** Purpose Timer SFRs.\r
-** 4] SFR names exactly match names in the device specific C "header" file\r
-** and the Assembly "include" file. Any changes to names in one of these\r
-** files, calls for similar changes in the other two.\r
-**\r
-* Revision History:\r
-** =================\r
-**-------------------------------------------------------------------------\r
-**Rev: Date: Details: Who:\r
-**-------------------------------------------------------------------------\r
-**1.0 11/29/01 Device linker provides from superset h vasuki\r
-**1.1 13 Dec 2001 Added PMD registers + some changes -do-\r
-**1.2 02 Dec 2002 CAN buffer correction -do-\r
-**1.3 13 Feb 2003 ADCSSLBits/ADPCFGBits Address correction -do-\r
-**1.4 05 May 2003 Initial release of linker scripts for rev -do-\r
-** B silicon with changes in CAN section\r
-**1.6 25 Nov 2003 CAN2 SFR bytes additions h vasuki\r
-**1.7 30 Jul 2004 ADCBUF0-ADCBUFF Address Correction h vasuki\r
-**1.7a 17 Dec 2004 CAN TXERRCNT Address Correction h vasuki\r
-**\r
-**-------------------------------------------------------------------------\r
-**\r
-**\r
-***************************************/\r
-\r
-\r
-/*=========================================================================\r
-** Register Definitions\r
-** (Core and Peripheral Registers in Data Space)\r
-**==========================================================================\r
-**\r
-**==========================================================================\r
-**\r
-** dsPIC Core Register Definitions\r
-**\r
-**=========================================================================*/\r
- WREG0 = 0x0000;\r
-_WREG0 = 0x0000;\r
- WREG1 = 0x0002;\r
-_WREG1 = 0x0002;\r
- WREG2 = 0x0004;\r
-_WREG2 = 0x0004;\r
- WREG3 = 0x0006;\r
-_WREG3 = 0x0006;\r
- WREG4 = 0x0008;\r
-_WREG4 = 0x0008;\r
- WREG5 = 0x000A;\r
-_WREG5 = 0x000A;\r
- WREG6 = 0x000C;\r
-_WREG6 = 0x000C;\r
- WREG7 = 0x000E;\r
-_WREG7 = 0x000E;\r
- WREG8 = 0x0010;\r
-_WREG8 = 0x0010;\r
- WREG9 = 0x0012;\r
-_WREG9 = 0x0012;\r
- WREG10 = 0x0014;\r
-_WREG10 = 0x0014;\r
- WREG11 = 0x0016;\r
-_WREG11 = 0x0016;\r
- WREG12 = 0x0018;\r
-_WREG12 = 0x0018;\r
- WREG13 = 0x001A;\r
-_WREG13 = 0x001A;\r
- WREG14 = 0x001C;\r
-_WREG14 = 0x001C;\r
- WREG15 = 0x001E;\r
-_WREG15 = 0x001E;\r
- SPLIM = 0x0020;\r
-_SPLIM = 0x0020;\r
- ACCAL = 0x0022;\r
-_ACCAL = 0x0022;\r
- ACCAH = 0x0024;\r
-_ACCAH = 0x0024;\r
- ACCAU = 0x0026;\r
-_ACCAU = 0x0026;\r
- ACCBL = 0x0028;\r
-_ACCBL = 0x0028;\r
- ACCBH = 0x002A;\r
-_ACCBH = 0x002A;\r
- ACCBU = 0x002C;\r
-_ACCBU = 0x002C;\r
- PCL = 0x002E;\r
-_PCL = 0x002E;\r
- PCH = 0x0030;\r
-_PCH = 0x0030;\r
- TBLPAG = 0x0032;\r
-_TBLPAG = 0x0032;\r
- PSVPAG = 0x0034;\r
-_PSVPAG = 0x0034;\r
- RCOUNT = 0x0036;\r
-_RCOUNT = 0x0036;\r
- DCOUNT = 0x0038;\r
-_DCOUNT = 0x0038;\r
- DOSTARTL = 0x003A;\r
-_DOSTARTL = 0x003A;\r
- DOSTARTH = 0x003C;\r
-_DOSTARTH = 0x003C;\r
- DOENDL = 0x003E;\r
-_DOENDL = 0x003E;\r
- DOENDH = 0x0040;\r
-_DOENDH = 0x0040;\r
- SR = 0x0042;\r
-_SR = 0x0042;\r
- CORCON = 0x0044;\r
-_CORCON = 0x0044;\r
- MODCON = 0x0046;\r
-_MODCON = 0x0046;\r
- XMODSRT = 0x0048;\r
-_XMODSRT = 0x0048;\r
- XMODEND = 0x004A;\r
-_XMODEND = 0x004A;\r
- YMODSRT = 0x004C;\r
-_YMODSRT = 0x004C;\r
- YMODEND = 0x004E;\r
-_YMODEND = 0x004E;\r
- XBREV = 0x0050;\r
-_XBREV = 0x0050;\r
- DISICNT = 0x0052;\r
-_DISICNT = 0x0052;\r
-\r
-\r
-\r
-/*==========================================================================\r
-**\r
-** Interrupt Controller Register Definitions\r
-**\r
-==========================================================================*/\r
- INTCON1 = 0x0080;\r
-_INTCON1 = 0x0080;\r
- INTCON2 = 0x0082;\r
-_INTCON2 = 0x0082;\r
- IFS0 = 0x0084;\r
-_IFS0 = 0x0084;\r
- IFS1 = 0x0086;\r
-_IFS1 = 0x0086;\r
- IFS2 = 0x0088;\r
-_IFS2 = 0x0088;\r
- IEC0 = 0x008C;\r
-_IEC0 = 0x008C;\r
- IEC1 = 0x008E;\r
-_IEC1 = 0x008E;\r
- IEC2 = 0x0090;\r
-_IEC2 = 0x0090;\r
- IPC0 = 0x0094;\r
-_IPC0 = 0x0094;\r
- IPC1 = 0x0096;\r
-_IPC1 = 0x0096;\r
- IPC2 = 0x0098;\r
-_IPC2 = 0x0098;\r
- IPC3 = 0x009A;\r
-_IPC3 = 0x009A;\r
- IPC4 = 0x009C;\r
-_IPC4 = 0x009C;\r
- IPC5 = 0x009E;\r
-_IPC5 = 0x009E;\r
- IPC6 = 0x00A0;\r
-_IPC6 = 0x00A0;\r
- IPC9 = 0x00A6;\r
-_IPC9 = 0x00A6;\r
- IPC10 = 0x00A8;\r
-_IPC10 = 0x00A8;\r
-\r
-\r
-\r
-/*==========================================================================\r
-**\r
-** Input Change Notification Module Register Definitions\r
-**\r
-===========================================================================*/\r
- CNEN1 = 0x00C0;\r
-_CNEN1 = 0x00C0;\r
- CNPU1 = 0x00C4;\r
-_CNPU1 = 0x00C4;\r
-\r
-\r
-\r
-/*=========================================================================\r
-**\r
-** Peripheral Register Definitions\r
-**\r
-===========================================================================*/\r
-/*=========================================================================\r
-**\r
-** Timer Module Register Definitions\r
-**\r
-===========================================================================*/\r
-/*--------------Timer 1 Module---------------------------------------------*/\r
- TMR1 = 0x0100;\r
-_TMR1 = 0x0100;\r
- PR1 = 0x0102;\r
-_PR1 = 0x0102;\r
- T1CON = 0x0104;\r
-_T1CON = 0x0104;\r
-\r
-/*--------------Timer2/3 Module--------------------------------------------*/\r
- TMR2 = 0x0106;\r
-_TMR2 = 0x0106;\r
- TMR3HLD = 0x0108;\r
-_TMR3HLD = 0x0108;\r
- TMR3 = 0x010A;\r
-_TMR3 = 0x010A;\r
- PR2 = 0x010C;\r
-_PR2 = 0x010C;\r
- PR3 = 0x010E;\r
-_PR3 = 0x010E;\r
- T2CON = 0x0110;\r
-_T2CON = 0x0110;\r
- T3CON = 0x0112;\r
-_T3CON = 0x0112;\r
-\r
-/*------------- Timer4/5 Module---------------------------------------------*/\r
- TMR4 = 0x0114;\r
-_TMR4 = 0x0114;\r
- TMR5HLD = 0x0116;\r
-_TMR5HLD = 0x0116;\r
- TMR5 = 0x0118;\r
-_TMR5 = 0x0118;\r
- PR4 = 0x011A;\r
-_PR4 = 0x011A;\r
- PR5 = 0x011C;\r
-_PR5 = 0x011C;\r
- T4CON = 0x011E;\r
-_T4CON = 0x011E;\r
- T5CON = 0x0120;\r
-_T5CON = 0x0120;\r
-\r
-/*=========================================================================\r
-**\r
-** Quadrature Encoder Interface Module Register Definitions\r
-**\r
-=========================================================================*/\r
- QEICON = 0x0122;\r
-_QEICON = 0x0122;\r
- DFLTCON = 0x0124;\r
-_DFLTCON = 0x0124;\r
- POSCNT = 0x0126;\r
-_POSCNT = 0x0126;\r
- MAXCNT = 0x0128;\r
-_MAXCNT = 0x0128;\r
-\r
-\r
-/*=========================================================================\r
-**\r
-** Input Capture Module Register Definitions\r
-**\r
-=========================================================================*/\r
- IC1BUF = 0x0140;\r
-_IC1BUF = 0x0140;\r
- IC1CON = 0x0142;\r
-_IC1CON = 0x0142;\r
- IC2BUF = 0x0144;\r
-_IC2BUF = 0x0144;\r
- IC2CON = 0x0146;\r
-_IC2CON = 0x0146;\r
- IC7BUF = 0x0158;\r
-_IC7BUF = 0x0158;\r
- IC7CON = 0x015A;\r
-_IC7CON = 0x015A;\r
- IC8BUF = 0x015C;\r
-_IC8BUF = 0x015C;\r
- IC8CON = 0x015E;\r
-_IC8CON = 0x015E;\r
-\r
-\r
-\r
-/*==========================================================================\r
-**\r
-** Output Compare Module Register Definitions\r
-**\r
-===========================================================================*/\r
- OC1RS = 0x0180;\r
-_OC1RS = 0x0180;\r
- OC1R = 0x0182;\r
-_OC1R = 0x0182;\r
- OC1CON = 0x0184;\r
-_OC1CON = 0x0184;\r
- OC2RS = 0x0186;\r
-_OC2RS = 0x0186;\r
- OC2R = 0x0188;\r
-_OC2R = 0x0188;\r
- OC2CON = 0x018A;\r
-_OC2CON = 0x018A;\r
-\r
-\r
-/*=========================================================================\r
-**\r
-** Motor Control PWM Module Register Definitions\r
-**\r
-=========================================================================*/\r
- PTCON = 0x01C0;\r
-_PTCON = 0x01C0;\r
- PTMR = 0x01C2;\r
-_PTMR = 0x01C2;\r
- PTPER = 0x01C4;\r
-_PTPER = 0x01C4;\r
- SEVTCMP = 0x01C6;\r
-_SEVTCMP = 0x01C6;\r
- PWMCON1 = 0x01C8;\r
-_PWMCON1 = 0x01C8;\r
- PWMCON2 = 0x01CA;\r
-_PWMCON2 = 0x01CA;\r
- DTCON1 = 0x01CC;\r
-_DTCON1 = 0x01CC;\r
- FLTACON = 0x01D0;\r
-_FLTACON = 0x01D0;\r
- OVDCON = 0x01D4;\r
-_OVDCON = 0x01D4;\r
- PDC1 = 0x01D6;\r
-_PDC1 = 0x01D6;\r
- PDC2 = 0x01D8;\r
-_PDC2 = 0x01D8;\r
- PDC3 = 0x01DA;\r
-_PDC3 = 0x01DA;\r
-\r
-\r
-\r
-/*=========================================================================\r
-**\r
-** Inter-Integrated Circuit(I2C) Module Register Definitions\r
-**\r
-==========================================================================*/\r
- I2CRCV = 0x0200;\r
-_I2CRCV = 0x0200;\r
- I2CTRN = 0x0202;\r
-_I2CTRN = 0x0202;\r
- I2CBRG = 0x0204;\r
-_I2CBRG = 0x0204;\r
- I2CCON = 0x0206;\r
-_I2CCON = 0x0206;\r
- I2CSTAT = 0x0208;\r
-_I2CSTAT = 0x0208;\r
- I2CADD = 0x020A;\r
-_I2CADD = 0x020A;\r
-\r
-/*==========================================================================\r
-**\r
-** Universal Asynchronous Receiver TransmitterUART Module\r
-** Register Definitions\r
-**\r
-==========================================================================*/\r
-/*------------------UART 1 Module-----------------------------------------*/\r
- U1MODE = 0x020C;\r
-_U1MODE = 0x020C;\r
- U1STA = 0x020E;\r
-_U1STA = 0x020E;\r
- U1TXREG = 0x0210;\r
-_U1TXREG = 0x0210;\r
- U1RXREG = 0x0212;\r
-_U1RXREG = 0x0212;\r
- U1BRG = 0x0214;\r
-_U1BRG = 0x0214;\r
-\r
-\r
-/*==========================================================================\r
-**\r
-** Serial Peripheral Interface(SPI) Module Register Definitions\r
-**\r
-==========================================================================*/\r
-/*-----------------SPI 1 Module-------------------------------------------*/\r
- SPI1STAT = 0x0220;\r
-_SPI1STAT = 0x0220;\r
- SPI1CON = 0x0222;\r
-_SPI1CON = 0x0222;\r
- SPI1BUF = 0x0224;\r
-_SPI1BUF = 0x0224;\r
-\r
-\r
-\r
-/*==========================================================================\r
-**\r
-** 10-bit A/D Converter 500 Ksps Module Register Definitions\r
-**\r
-==========================================================================*/\r
- ADCBUF0 = 0x0280;\r
-_ADCBUF0 = 0x0280;\r
- ADCBUF1 = 0x0282;\r
-_ADCBUF1 = 0x0282;\r
- ADCBUF2 = 0x0284;\r
-_ADCBUF2 = 0x0284;\r
- ADCBUF3 = 0x0286;\r
-_ADCBUF3 = 0x0286;\r
- ADCBUF4 = 0x0288;\r
-_ADCBUF4 = 0x0288;\r
- ADCBUF5 = 0x028A;\r
-_ADCBUF5 = 0x028A;\r
- ADCBUF6 = 0x028C;\r
-_ADCBUF6 = 0x028C;\r
- ADCBUF7 = 0x028E;\r
-_ADCBUF7 = 0x028E;\r
- ADCBUF8 = 0x0290;\r
-_ADCBUF8 = 0x0290;\r
- ADCBUF9 = 0x0292;\r
-_ADCBUF9 = 0x0292;\r
- ADCBUFA = 0x0294;\r
-_ADCBUFA = 0x0294;\r
- ADCBUFB = 0x0296;\r
-_ADCBUFB = 0x0296;\r
- ADCBUFC = 0x0298;\r
-_ADCBUFC = 0x0298;\r
- ADCBUFD = 0x029A;\r
-_ADCBUFD = 0x029A;\r
- ADCBUFE = 0x029C;\r
-_ADCBUFE = 0x029C;\r
- ADCBUFF = 0x029E;\r
-_ADCBUFF = 0x029E;\r
- ADCON1 = 0x02A0;\r
-_ADCON1 = 0x02A0;\r
- ADCON2 = 0x02A2;\r
-_ADCON2 = 0x02A2;\r
- ADCON3 = 0x02A4;\r
-_ADCON3 = 0x02A4;\r
- ADCHS = 0x02A6;\r
-_ADCHS = 0x02A6;\r
- ADPCFG = 0x02A8;\r
-_ADPCFG = 0x02A8;\r
- ADCSSL = 0x02AA;\r
-_ADCSSL = 0x02AA;\r
-\r
-/*==========================================================================\r
-**\r
-** General Purpose I/O Port Register Definitions\r
-**\r
-==========================================================================*/\r
- TRISB = 0x02C6;\r
-_TRISB = 0x02C6;\r
- PORTB = 0x02C8;\r
-_PORTB = 0x02C8;\r
- LATB = 0x02CA;\r
-_LATB = 0x02CA;\r
-\r
- TRISC = 0x02CC;\r
-_TRISC = 0x02CC;\r
- PORTC = 0x02CE;\r
-_PORTC = 0x02CE;\r
- LATC = 0x02D0;\r
-_LATC = 0x02D0;\r
-\r
- TRISD = 0x02D2;\r
-_TRISD = 0x02D2;\r
- PORTD = 0x02D4;\r
-_PORTD = 0x02D4;\r
- LATD = 0x02D6;\r
-_LATD = 0x02D6;\r
-\r
- TRISE = 0x02D8;\r
-_TRISE = 0x02D8;\r
- PORTE = 0x02DA;\r
-_PORTE = 0x02DA;\r
- LATE = 0x02DC;\r
-_LATE = 0x02DC;\r
-\r
- TRISF = 0x02DE;\r
-\r
-_TRISF = 0x02DE;\r
- PORTF = 0x02E0;\r
-_PORTF = 0x02E0;\r
- LATF = 0x02E2;\r
-_LATF = 0x02E2;\r
-\r
-\r
-\r
-/*==========================================================================\r
-**\r
-** Controller Area Network Module Register Definitions\r
-** (for CAN Modules 1 and 2)\r
-==========================================================================*/\r
-\r
-/*==========================================================================\r
-**\r
-** CAN1 register definitions\r
-**\r
-==========================================================================*/\r
-C1RXF0SID = 0x0300;\r
-_C1RXF0SID = 0x0300;\r
-C1RXF0EIDH = 0x0302;\r
-_C1RXF0EIDH = 0x0302;\r
-C1RXF0EIDL = 0x0304;\r
-_C1RXF0EIDL = 0x0304;\r
-C1RXF1SID = 0x0308;\r
-_C1RXF1SID = 0x0308;\r
-C1RXF1EIDH = 0x030A;\r
-_C1RXF1EIDH = 0x030A;\r
-C1RXF1EIDL = 0x030C;\r
-_C1RXF1EIDL = 0x030C;\r
-C1RXF2SID = 0x0310;\r
-_C1RXF2SID = 0x0310;\r
-C1RXF2EIDH = 0x0312;\r
-_C1RXF2EIDH = 0x0312;\r
-C1RXF2EIDL = 0x0314;\r
-_C1RXF2EIDL = 0x0314;\r
-C1RXF3SID = 0x0318;\r
-_C1RXF3SID = 0x0318;\r
-C1RXF3EIDH = 0x031A;\r
-_C1RXF3EIDH = 0x031A;\r
-C1RXF3EIDL = 0x031C;\r
-_C1RXF3EIDL = 0x031C;\r
-C1RXF4SID = 0x0320;\r
-_C1RXF4SID = 0x0320;\r
-C1RXF4EIDH = 0x0322;\r
-_C1RXF4EIDH = 0x0322;\r
-C1RXF4EIDL = 0x0324;\r
-_C1RXF4EIDL = 0x0324;\r
-C1RXF5SID = 0x0328;\r
-_C1RXF5SID = 0x0328;\r
-C1RXF5EIDH = 0x032A;\r
-_C1RXF5EIDH = 0x032A;\r
-C1RXF5EIDL = 0x032C;\r
-_C1RXF5EIDL = 0x032C;\r
-C1RXM0SID = 0x0330;\r
-_C1RXM0SID = 0x0330;\r
-C1RXM0EIDH = 0x0332;\r
-_C1RXM0EIDH = 0x0332;\r
-C1RXM0EIDL = 0x0334;\r
-_C1RXM0EIDL = 0x0334;\r
-C1RXM1SID = 0x0338;\r
-_C1RXM1SID = 0x0338;\r
-C1RXM1EIDH = 0x033A;\r
-_C1RXM1EIDH = 0x033A;\r
-C1RXM1EIDL = 0x033C;\r
-_C1RXM1EIDL = 0x033C;\r
-C1TX2SID = 0x0340;\r
-_C1TX2SID = 0x0340;\r
-C1TX2EID = 0x0342;\r
-_C1TX2EID = 0x0342;\r
-C1TX2DLC = 0x0344;\r
-_C1TX2DLC = 0x0344;\r
-C1TX2B1 = 0x0346;\r
-_C1TX2B1 = 0x0346;\r
-C1TX2B2 = 0x0348;\r
-_C1TX2B2 = 0x0348;\r
-C1TX2B3 = 0x034A;\r
-_C1TX2B3 = 0x034A;\r
-C1TX2B4 = 0x034C;\r
-_C1TX2B4 = 0x034C;\r
-C1TX2CON = 0x034E;\r
-_C1TX2CON = 0x034E;\r
-C1TX1SID = 0x0350;\r
-_C1TX1SID = 0x0350;\r
-C1TX1EID = 0x0352;\r
-_C1TX1EID = 0x0352;\r
-C1TX1DLC = 0x0354;\r
-_C1TX1DLC = 0x0354;\r
-C1TX1B1 = 0x0356;\r
-_C1TX1B1 = 0x0356;\r
-C1TX1B2 = 0x0358;\r
-_C1TX1B2 = 0x0358;\r
-C1TX1B3 = 0x035A;\r
-_C1TX1B3 = 0x035A;\r
-C1TX1B4 = 0x035C;\r
-_C1TX1B4 = 0x035C;\r
-C1TX1CON = 0x035E;\r
-_C1TX1CON = 0x035E;\r
-C1TX0SID = 0x0360;\r
-_C1TX0SID = 0x0360;\r
-C1TX0EID = 0x0362;\r
-_C1TX0EID = 0x0362;\r
-C1TX0DLC = 0x0364;\r
-_C1TX0DLC = 0x0364;\r
-C1TX0B1 = 0x0366;\r
-_C1TX0B1 = 0x0366;\r
-C1TX0B2 = 0x0368;\r
-_C1TX0B2 = 0x0368;\r
-C1TX0B3 = 0x036A;\r
-_C1TX0B3 = 0x036A;\r
-C1TX0B4 = 0x036C;\r
-_C1TX0B4 = 0x036C;\r
-C1TX0CON = 0x036E;\r
-_C1TX0CON = 0x036E;\r
-C1RX1SID = 0x0370;\r
-_C1RX1SID = 0x0370;\r
-C1RX1EID = 0x0372;\r
-_C1RX1EID = 0x0372;\r
-C1RX1DLC = 0x0374;\r
-_C1RX1DLC = 0x0374;\r
-C1RX1B1 = 0x0376;\r
-_C1RX1B1 = 0x0376;\r
-C1RX1B2 = 0x0378;\r
-_C1RX1B2 = 0x0378;\r
-C1RX1B3 = 0x037A;\r
-_C1RX1B3 = 0x037A;\r
-C1RX1B4 = 0x037C;\r
-_C1RX1B4 = 0x037C;\r
-C1RX1CON = 0x037E;\r
-_C1RX1CON = 0x037E;\r
-C1RX0SID = 0x0380;\r
-_C1RX0SID = 0x0380;\r
-C1RX0EID = 0x0382;\r
-_C1RX0EID = 0x0382;\r
-C1RX0DLC = 0x0384;\r
-_C1RX0DLC = 0x0384;\r
-C1RX0B1 = 0x0386;\r
-_C1RX0B1 = 0x0386;\r
-C1RX0B2 = 0x0388;\r
-_C1RX0B2 = 0x0388;\r
-C1RX0B3 = 0x038A;\r
-_C1RX0B3 = 0x038A;\r
-C1RX0B4 = 0x038C;\r
-_C1RX0B4 = 0x038C;\r
-C1RX0CON = 0x038E;\r
-_C1RX0CON = 0x038E;\r
-C1CTRL = 0x0390;\r
-_C1CTRL = 0x0390;\r
-C1CFG1 = 0x0392;\r
-_C1CFG1 = 0x0392;\r
-C1CFG2 = 0x0394;\r
-_C1CFG2 = 0x0394;\r
-C1INTF = 0x0396;\r
-_C1INTF = 0x0396;\r
-C1INTE = 0x0398;\r
-_C1INTE = 0x0398;\r
-C1EC = 0x039A;\r
-_C1EC = 0x039A;\r
-C1RERRCNT = 0x039A;\r
-_C1RERRCNT = 0x039A;\r
-C1TERRCNT = 0x039B;\r
-_C1TERRCNT = 0x039B;\r
-\r
-/*==========================================================================\r
-**\r
-** System Integration Block Registers\r
-**\r
-==========================================================================*/\r
- RCON = 0x0740;\r
-_RCON = 0x0740;\r
- OSCCON = 0x0742;\r
-_OSCCON = 0x0742;\r
-\r
-/*==========================================================================\r
-**\r
-** Non Volatile Memory Registers\r
-**\r
-==========================================================================*/\r
- NVMCON = 0x0760;\r
-_NVMCON = 0x0760;\r
- NVMADR = 0x0762;\r
-_NVMADR = 0x0762;\r
- NVMADRU = 0x0764;\r
-_NVMADRU = 0x0764;\r
- NVMKEY = 0x0766;\r
-_NVMKEY = 0x0766;\r
-\r
-/*==========================================================================\r
-**\r
-** Peripheral Module Disable Registers\r
-**\r
-==========================================================================*/\r
- PMD1 = 0x0770;\r
-_PMD1 = 0x0770;\r
- PMD2 = 0x0772;\r
-_PMD2 = 0x0772;\r
- PMD3 = 0x0774;\r
-_PMD3 = 0x0774;\r
-/*\r
-**End of SFR Definitions required for both C and Assembly files\r
-*/\r
-\r
-\r
-/*=========================================================================\r
-**\r
-**Start of Additional SFR Definitions that are required specifically\r
-**for the C header file.\r
-**\r
-==========================================================================*/\r
- ACCA = 0x0022;\r
-_ACCA = 0x0022;\r
- ACCB = 0x0028;\r
-_ACCB = 0x0028;\r
- SRbits = 0x0042;\r
-_SRbits = 0x0042;\r
- CORCONbits = 0x0044;\r
-_CORCONbits = 0x0044;\r
- MODCONbits = 0x0046;\r
-_MODCONbits = 0x0046;\r
- XBREVbits = 0x0050;\r
-_XBREVbits = 0x0050;\r
- DISICNTbits = 0x0052;\r
-_DISICNTbits = 0x0052;\r
- INTCON1bits = 0x0080;\r
-_INTCON1bits = 0x0080;\r
- INTCON2bits = 0x0082;\r
-_INTCON2bits = 0x0082;\r
- IFS0bits = 0x0084;\r
-_IFS0bits = 0x0084;\r
- IFS1bits = 0x0086;\r
-_IFS1bits = 0x0086;\r
- IFS2bits = 0x0088;\r
-_IFS2bits = 0x0088;\r
- IEC0bits = 0x008C;\r
-_IEC0bits = 0x008C;\r
- IEC1bits = 0x008E;\r
-_IEC1bits = 0x008E;\r
- IEC2bits = 0x0090;\r
-_IEC2bits = 0x0090;\r
- IPC0bits = 0x0094;\r
-_IPC0bits = 0x0094;\r
- IPC1bits = 0x0096;\r
-_IPC1bits = 0x0096;\r
- IPC2bits = 0x0098;\r
-_IPC2bits = 0x0098;\r
- IPC3bits = 0x009A;\r
-_IPC3bits = 0x009A;\r
- IPC4bits = 0x009C;\r
-_IPC4bits = 0x009C;\r
- IPC5bits = 0x009E;\r
-_IPC5bits = 0x009E;\r
- IPC6bits = 0x00A0;\r
-_IPC6bits = 0x00A0;\r
- IPC9bits = 0x00A6;\r
-_IPC9bits = 0x00A6;\r
- IPC10bits = 0x00A8;\r
-_IPC10bits = 0x00A8;\r
- IPC11bits = 0x00AA;\r
-_IPC11bits = 0x00AA;\r
- CNEN1bits = 0x00C0;\r
-_CNEN1bits = 0x00C0;\r
- CNPU1bits = 0x00C4;\r
-_CNPU1bits = 0x00C4;\r
- T1CONbits = 0x0104;\r
-_T1CONbits = 0x0104;\r
- T2CONbits = 0x0110;\r
-_T2CONbits = 0x0110;\r
- T3CONbits = 0x0112;\r
-_T3CONbits = 0x0112;\r
- T4CONbits = 0x011E;\r
-_T4CONbits = 0x011E;\r
- T5CONbits = 0x0120;\r
-_T5CONbits = 0x0120;\r
- QEICONbits = 0x0122;\r
-_QEICONbits = 0x0122;\r
- DFLTCONbits = 0x0124;\r
-_DFLTCONbits = 0x0124;\r
- IC1CONbits = 0x0142;\r
-_IC1CONbits = 0x0142;\r
- IC2CONbits = 0x0146;\r
-_IC2CONbits = 0x0146;\r
- IC7CONbits = 0x015A;\r
-_IC7CONbits = 0x015A;\r
- IC8CONbits = 0x015E;\r
-_IC8CONbits = 0x015E;\r
- OC1CONbits = 0x0184;\r
-_OC1CONbits = 0x0184;\r
- OC2CONbits = 0x018A;\r
-_OC2CONbits = 0x018A;\r
- PTCONbits = 0x01C0;\r
-_PTCONbits = 0x01C0;\r
- PTMRbits = 0x01C2;\r
-_PTMRbits = 0x01C2;\r
- PTPERbits = 0x01C4;\r
-_PTPERbits = 0x01C4;\r
- SEVTCMPbits = 0x01C6;\r
-_SEVTCMPbits = 0x01C6;\r
- PWMCON1bits = 0x01C8;\r
-_PWMCON1bits = 0x01C8;\r
- PWMCON2bits = 0x01CA;\r
-_PWMCON2bits = 0x01CA;\r
- DTCON1bits = 0x01CC;\r
-_DTCON1bits = 0x01CC;\r
- FLTACONbits = 0x01D0;\r
-_FLTACONbits = 0x01D0;\r
- OVDCONbits = 0x01D4;\r
-_OVDCONbits = 0x01D4;\r
- I2CRCVbits = 0x0200;\r
-_I2CRCVbits = 0x0200;\r
- I2CTRNbits = 0x0202;\r
-_I2CTRNbits = 0x0202;\r
- I2CBRGbits = 0x0204;\r
-_I2CBRGbits = 0x0204;\r
- I2CCONbits = 0x0206;\r
-_I2CCONbits = 0x0206;\r
- I2CSTATbits = 0x0208;\r
-_I2CSTATbits = 0x0208;\r
- I2CADDbits = 0x020A;\r
-_I2CADDbits = 0x020A;\r
- U1MODEbits = 0x020C;\r
-_U1MODEbits = 0x020C;\r
- U1STAbits = 0x020E;\r
-_U1STAbits = 0x020E;\r
- U1TXREGbits = 0x0210;\r
-_U1TXREGbits = 0x0210;\r
- U1RXREGbits = 0x0212;\r
-_U1RXREGbits = 0x0212;\r
- SPI1STATbits = 0x0220;\r
-_SPI1STATbits = 0x0220;\r
- SPI1CONbits = 0x0222;\r
-_SPI1CONbits = 0x0222;\r
- ADCON1bits = 0x02A0;\r
-_ADCON1bits = 0x02A0;\r
- ADCON2bits = 0x02A2;\r
-_ADCON2bits = 0x02A2;\r
- ADCON3bits = 0x02A4;\r
-_ADCON3bits = 0x02A4;\r
- ADCHSbits = 0x02A6;\r
-_ADCHSbits = 0x02A6;\r
- ADPCFGbits = 0x02A8;\r
-_ADPCFGbits = 0x02A8;\r
- ADCSSLbits = 0x02AA;\r
-_ADCSSLbits = 0x02AA;\r
- TRISBbits = 0x02C6;\r
-_TRISBbits = 0x02C6;\r
- PORTBbits = 0x02C8;\r
-_PORTBbits = 0x02C8;\r
- LATBbits = 0x02CA;\r
-_LATBbits = 0x02CA;\r
- TRISCbits = 0x02CC;\r
-_TRISCbits = 0x02CC;\r
- PORTCbits = 0x02CE;\r
-_PORTCbits = 0x02CE;\r
- LATCbits = 0x02D0;\r
-_LATCbits = 0x02D0;\r
- TRISDbits = 0x02D2;\r
-_TRISDbits = 0x02D2;\r
- PORTDbits = 0x02D4;\r
-_PORTDbits = 0x02D4;\r
- LATDbits = 0x02D6;\r
-_LATDbits = 0x02D6;\r
- TRISEbits = 0x02D8;\r
-_TRISEbits = 0x02D8;\r
- PORTEbits = 0x02DA;\r
-_PORTEbits = 0x02DA;\r
- LATEbits = 0x02DC;\r
-_LATEbits = 0x02DC;\r
- TRISFbits = 0x02DE;\r
-_TRISFbits = 0x02DE;\r
- PORTFbits = 0x02E0;\r
-_PORTFbits = 0x02E0;\r
-\r
- LATFbits = 0x02E2;\r
-_LATFbits = 0x02E2;\r
- C1RXF0SIDbits = 0x0300;\r
-_C1RXF0SIDbits = 0x0300;\r
- C1RXF0EIDHbits = 0x0302;\r
-_C1RXF0EIDHbits = 0x0302;\r
- C1RXF0EIDLbits = 0x0304;\r
-_C1RXF0EIDLbits = 0x0304;\r
- C1RXF1SIDbits = 0x0308;\r
-_C1RXF1SIDbits = 0x0308;\r
- C1RXF1EIDHbits = 0x030A;\r
-_C1RXF1EIDHbits = 0x030A;\r
- C1RXF1EIDLbits = 0x030C;\r
-_C1RXF1EIDLbits = 0x030C;\r
- C1RXF2SIDbits = 0x0310;\r
-_C1RXF2SIDbits = 0x0310;\r
- C1RXF2EIDHbits = 0x0312;\r
-_C1RXF2EIDHbits = 0x0312;\r
- C1RXF2EIDLbits = 0x0314;\r
-_C1RXF2EIDLbits = 0x0314;\r
- C1RXF3SIDbits = 0x0318;\r
-_C1RXF3SIDbits = 0x0318;\r
- C1RXF3EIDHbits = 0x031A;\r
-_C1RXF3EIDHbits = 0x031A;\r
- C1RXF3EIDLbits = 0x031C;\r
-_C1RXF3EIDLbits = 0x031C;\r
- C1RXF4SIDbits = 0x0320;\r
-_C1RXF4SIDbits = 0x0320;\r
- C1RXF4EIDHbits = 0x0322;\r
-_C1RXF4EIDHbits = 0x0322;\r
- C1RXF4EIDLbits = 0x0324;\r
-_C1RXF4EIDLbits = 0x0324;\r
- C1RXF5SIDbits = 0x0328;\r
-_C1RXF5SIDbits = 0x0328;\r
- C1RXF5EIDHbits = 0x032A;\r
-_C1RXF5EIDHbits = 0x032A;\r
- C1RXF5EIDLbits = 0x032C;\r
-_C1RXF5EIDLbits = 0x032C;\r
- C1RXM0SIDbits = 0x0330;\r
-_C1RXM0SIDbits = 0x0330;\r
- C1RXM0EIDHbits = 0x0332;\r
-_C1RXM0EIDHbits = 0x0332;\r
- C1RXM0EIDLbits = 0x0334;\r
-_C1RXM0EIDLbits = 0x0334;\r
- C1RXM1SIDbits = 0x0338;\r
-_C1RXM1SIDbits = 0x0338;\r
- C1RXM1EIDHbits = 0x033A;\r
-_C1RXM1EIDHbits = 0x033A;\r
- C1RXM1EIDLbits = 0x033C;\r
-_C1RXM1EIDLbits = 0x033C;\r
- C1TX2SIDbits = 0x0340;\r
-_C1TX2SIDbits = 0x0340;\r
- C1TX2EIDbits = 0x0342;\r
-_C1TX2EIDbits = 0x0342;\r
- C1TX2DLCbits = 0x0344;\r
-_C1TX2DLCbits = 0x0344;\r
- C1TX2B1bits = 0x0346;\r
-_C1TX2B1bits = 0x0346;\r
- C1TX2B2bits = 0x0348;\r
-_C1TX2B2bits = 0x0348;\r
- C1TX2B3bits = 0x034A;\r
-_C1TX2B3bits = 0x034A;\r
- C1TX2B4bits = 0x034C;\r
-_C1TX2B4bits = 0x034C;\r
- C1TX2CONbits = 0x034E;\r
-_C1TX2CONbits = 0x034E;\r
- C1TX1SIDbits = 0x0350;\r
-_C1TX1SIDbits = 0x0350;\r
- C1TX1EIDbits = 0x0352;\r
-_C1TX1EIDbits = 0x0352;\r
- C1TX1DLCbits = 0x0354;\r
-_C1TX1DLCbits = 0x0354;\r
- C1TX1B1bits = 0x0356;\r
-_C1TX1B1bits = 0x0356;\r
- C1TX1B2bits = 0x0358;\r
-_C1TX1B2bits = 0x0358;\r
- C1TX1B3bits = 0x035A;\r
-_C1TX1B3bits = 0x035A;\r
- C1TX1B4bits = 0x035C;\r
-_C1TX1B4bits = 0x035C;\r
- C1TX1CONbits = 0x035E;\r
-_C1TX1CONbits = 0x035E;\r
- C1TX0SIDbits = 0x0360;\r
-_C1TX0SIDbits = 0x0360;\r
- C1TX0EIDbits = 0x0362;\r
-_C1TX0EIDbits = 0x0362;\r
- C1TX0DLCbits = 0x0364;\r
-_C1TX0DLCbits = 0x0364;\r
- C1TX0B1bits = 0x0366;\r
-_C1TX0B1bits = 0x0366;\r
- C1TX0B2bits = 0x0368;\r
-_C1TX0B2bits = 0x0368;\r
- C1TX0B3bits = 0x036A;\r
-_C1TX0B3bits = 0x036A;\r
- C1TX0B4bits = 0x036C;\r
-_C1TX0B4bits = 0x036C;\r
- C1TX0CONbits = 0x036E;\r
-_C1TX0CONbits = 0x036E;\r
- C1RX1SIDbits = 0x0370;\r
-_C1RX1SIDbits = 0x0370;\r
- C1RX1EIDbits = 0x0372;\r
-_C1RX1EIDbits = 0x0372;\r
- C1RX1DLCbits = 0x0374;\r
-_C1RX1DLCbits = 0x0374;\r
- C1RX1B1bits = 0x0376;\r
-_C1RX1B1bits = 0x0376;\r
- C1RX1B2bits = 0x0378;\r
-_C1RX1B2bits = 0x0378;\r
- C1RX1B3bits = 0x037A;\r
-_C1RX1B3bits = 0x037A;\r
- C1RX1B4bits = 0x037C;\r
-_C1RX1B4bits = 0x037C;\r
- C1RX1CONbits = 0x037E;\r
-_C1RX1CONbits = 0x037E;\r
- C1RX0SIDbits = 0x0380;\r
-_C1RX0SIDbits = 0x0380;\r
- C1RX0EIDbits = 0x0382;\r
-_C1RX0EIDbits = 0x0382;\r
- C1RX0DLCbits = 0x0384;\r
-_C1RX0DLCbits = 0x0384;\r
- C1RX0B1bits = 0x0386;\r
-_C1RX0B1bits = 0x0386;\r
- C1RX0B2bits = 0x0388;\r
-_C1RX0B2bits = 0x0388;\r
- C1RX0B3bits = 0x038A;\r
-_C1RX0B3bits = 0x038A;\r
- C1RX0B4bits = 0x038C;\r
-_C1RX0B4bits = 0x038C;\r
- C1RX0CONbits = 0x038E;\r
-_C1RX0CONbits = 0x038E;\r
- C1CTRLbits = 0x0390;\r
-_C1CTRLbits = 0x0390;\r
- C1CFG1bits = 0x0392;\r
-_C1CFG1bits = 0x0392;\r
- C1CFG2bits = 0x0394;\r
-_C1CFG2bits = 0x0394;\r
- C1INTFbits = 0x0396;\r
-_C1INTFbits = 0x0396;\r
- C1INTEbits = 0x0398;\r
-_C1INTEbits = 0x0398;\r
- C1ECbits = 0x039A;\r
-_C1ECbits = 0x039A;\r
-\r
- RCONbits = 0x0740;\r
-_RCONbits = 0x0740;\r
- OSCCONbits = 0x742;\r
-_OSCCONbits = 0x742;\r
- NVMCONbits = 0x0760;\r
-_NVMCONbits = 0x0760;\r
- PMD1bits = 0x0770;\r
-_PMD1bits = 0x0770;\r
- PMD2bits = 0x0772;\r
-_PMD2bits = 0x0772;\r
- PMD3bits = 0x0774;\r
-_PMD3bits = 0x0774;\r
-/*\r
-**end of SFR definitions required for C header\r
-*/\r
-\r
-/* SFR base address definitions for various peripherals */\r
-\r
- IC1 = 0x0140;\r
-_IC1 = 0x0140;\r
- IC2 = 0x0144;\r
-_IC2 = 0x0144;\r
- IC3 = 0x0148;\r
-_IC3 = 0x0148;\r
- IC4 = 0x014C;\r
-_IC4 = 0x014C;\r
-\r
- OC1 = 0x0180;\r
-_OC1 = 0x0180;\r
- OC2 = 0x0186;\r
-_OC2 = 0x0186;\r
-\r
- UART1 = 0x020C;\r
-_UART1 = 0x020C;\r
-\r
- SPI1 = 0x0220;\r
-_SPI1 = 0x0220;\r
-\r
- CAN1 = 0x0300;\r
-_CAN1 = 0x0300;\r
-\r
-/*=========================================================================\r
-**end of SFR definitions required in Data Space\r
-*========================================================================*/\r
-\r
+++ /dev/null
-\r
-/*-------------------------------------------------------------------------\r
- *\r
- * MPLAB-C30 dsPIC30F4012 processor header\r
- *\r
- * (c) Copyright 2005 Microchip Technology, All rights reserved\r
- *\r
- * File Description / Notes:\r
- * =========================\r
- * 1] This header file defines special function registers (SFR), and useful \r
- * macros for the dsPIC30Fxxxx Family of Digital Signal\r
- * Controllers (also referred to as the dsPIC). \r
- * 2] The register and bit names used in this file match the \r
- * dsPIC30Fxxxx data sheets as closely as possible. \r
- * 3] The memory locations of the registers defined in this header file are\r
- * specified in the respective linker scripts.\r
- * 4] SFR definitions are listed in the ascending order of memory addresses\r
- * and are grouped based on the module they belong to. For e.g., WREG10\r
- * is listed before ACCAL, and the Core SFRs are grouped separately\r
- * from the Interrupt Controller SFRs or the General Purpose Timer SFRs.\r
- * \r
- * Revision History:\r
- * =================\r
- * --------------------------------------------------------------------------\r
- * Rev: Date: Details: Who:\r
- * --------------------------------------------------------------------------\r
- * 2.0 23 Apr 2003 New file P Sinha\r
- * 2.0a 24 Apr 2003 Added CEID bit P Sinha\r
- * 2.0b 30 Apr 2003 Removed suffix 'B' from device number P Sinha\r
- * 2.0c 2 May 2003 'H' suffix added to CiRXFnEID/CiRXMnEID P Sinha\r
- * 2.1 2 Jun 2003 Relocated CANCAP bit to CxCTRL P Sinha\r
- * 2.2 17 Jun 2003 Renamed CONV bit to DONE P Sinha\r
- * 2.3 20 Jun 2003 Corrections in Config Fuses comments P Sinha\r
- * 2.3a 23 Jun 2003 Typos in CAN structure corrected P Sinha\r
- * 2.3b 5 Aug 2003 Added TUN1-4 bits in OSCCON P Sinha\r
- * 2.3c 18 Sep 2003 DFLTCON changes P Sinha\r
- * 2.4 10 Oct 2003 Added macros for data allocation and ISRs P Sinha\r
- * 2.5 25 Nov 2003 Renamed TUN1-4 bits to TUNF0-3 P Sinha\r
- * 3.0 30 Mar 2004 Added defines for unique SFR bit names P Sinha\r
- * 3.1 5 Apr 2004 Added underscore before SFR bit labels P Sinha\r
- * 3.1a 8 Apr 2004 Added config macros for FRC w/ PLL modes P Sinha\r
- * 3.2 11 Apr 2004 Enhanced config macro usage examples P Sinha\r
- * 3.3 14 Apr 2004 Corrected a typo in the _U1RXIE bit label P Sinha\r
- * 4.0 28 Sep 2004 Changed data allocation macro definitions P Sinha\r
- * 4.1 22 Dec 2004 Corrected a typo in the _U1RXIE definition P Sinha\r
- * 4.1a 14 Mar 2005 Removed LVD definitions P Sinha\r
- * 4.2 4 Apr 2005 Renamed EC_IO to ECIO and ERC_IO to ERCIO P Sinha\r
- * 4.2a 27 Jun 2005 Fixed typos in comments regarding macros G McCar\r
- * 4.3 1 Jul 2005 Updated section syntax in config macros P Sinha\r
- * --------------------------------------------------------------------------\r
- *\r
- * ------------------------------------------------------------------------*/\r
-\r
-#ifndef __30F4012_H\r
-#define __30F4012_H\r
-\r
-/* ------------------------- */ \r
-/* Core Register Definitions */\r
-/* ------------------------- */\r
-\r
-/* W registers W0-W15 */\r
-extern volatile unsigned int WREG0 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG1 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG2 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG3 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG4 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG5 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG6 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG7 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG8 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG9 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG10 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG11 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG12 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG13 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG14 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-extern volatile unsigned int WREG15 __attribute__((__sfr__,__deprecated__,__unsafe__));\r
-\r
-/* SPLIM: Stack Pointer Limit */\r
-extern volatile unsigned int SPLIM __attribute__((__sfr__));\r
-\r
-/* Alternative access structure for the 40-bit accumulators */\r
-typedef struct tagACC {\r
- unsigned int L;\r
- unsigned int H;\r
- unsigned char U;\r
-} ACC;\r
-\r
-/* Acc A<15:0> */\r
-extern volatile unsigned int ACCAL __attribute__((__sfr__));\r
-\r
-/* Acc A<31:16> */\r
-extern volatile unsigned int ACCAH __attribute__((__sfr__));\r
-\r
-/* Acc A<39:32> */\r
-extern volatile unsigned char ACCAU __attribute__((__sfr__));\r
-\r
-/* Acc A defined as a structure consisting of the 3 parts */\r
-extern volatile ACC ACCA __attribute__((__sfr__));\r
-\r
-/* Acc B<15:0> */\r
-extern volatile unsigned int ACCBL __attribute__((__sfr__));\r
-\r
-/* Acc B<31:16> */\r
-extern volatile unsigned int ACCBH __attribute__((__sfr__));\r
-\r
-/* Acc B<39:32> */\r
-extern volatile unsigned char ACCBU __attribute__((__sfr__));\r
-\r
-/* Acc B defined as a structure consisting of the 3 parts */\r
-extern volatile ACC ACCB __attribute__((__sfr__));\r
-\r
-/* PCL: Program Counter low word */ \r
-extern volatile unsigned int PCL __attribute__((__sfr__));\r
-\r
-/* PCH: Program Counter high byte */\r
-extern volatile unsigned char PCH __attribute__((__sfr__));\r
-\r
-/* TBLPAG: Table Page Register */\r
-extern volatile unsigned char TBLPAG __attribute__((__sfr__));\r
-\r
-/* PSVPAG: Program Space Visibility Page Register */\r
-extern volatile unsigned char PSVPAG __attribute__((__sfr__));\r
-\r
-/* RCOUNT: REPEAT loop count */\r
-extern volatile unsigned int RCOUNT __attribute__((__sfr__));\r
-\r
-/* DCOUNT: DO loop count */\r
-extern volatile unsigned int DCOUNT __attribute__((__sfr__));\r
-\r
-/* DOSTARTL: DO loop start address bits <15:0> */\r
-extern volatile unsigned int DOSTARTL __attribute__((__sfr__));\r
-\r
-/* DOSTARTH: DO loop start address bits <23:16> */\r
-extern volatile unsigned int DOSTARTH __attribute__((__sfr__));\r
-\r
-/* DOENDL: DO loop end address bits <15:0> */\r
-extern volatile unsigned int DOENDL __attribute__((__sfr__));\r
-\r
-/* DOENDH: DO loop end address bits <23:16> */\r
-extern volatile unsigned int DOENDH __attribute__((__sfr__));\r
-\r
-/* SR: Status Register */\r
-extern volatile unsigned int SR __attribute__((__sfr__));\r
-typedef struct tagSRBITS {\r
- unsigned C :1; /* Carry flag */\r
- unsigned Z :1; /* Sticky Zero flag */\r
- unsigned OV :1; /* Overflow flag */ \r
- unsigned N :1; /* Negative flag */\r
- unsigned RA :1; /* REPEAT loop active flag */\r
- unsigned IPL :3; /* CPU Interrupt Priority Level */\r
- unsigned DC :1; /* Digit Carry flag */\r
- unsigned DA :1; /* DO loop active flag */\r
- unsigned SAB :1; /* Combined A/B saturation flag */\r
- unsigned OAB :1; /* Combined A/B overflow flag */ \r
- unsigned SB :1; /* Acc B saturation flag */\r
- unsigned SA :1; /* Acc A saturation flag */\r
- unsigned OB :1; /* Acc B overflow flag */\r
- unsigned OA :1; /* Acc A overflow flag */\r
-} SRBITS;\r
-extern volatile SRBITS SRbits __attribute__((__sfr__));\r
-\r
-/* CORCON: CPU Mode control Register */\r
-extern volatile unsigned int CORCON __attribute__((__sfr__));\r
-typedef struct tagCORCONBITS {\r
- unsigned IF :1; /* Integer/Fractional mode */ \r
- unsigned RND :1; /* Rounding mode */\r
- unsigned PSV :1; /* Program Space Visibility enable */\r
- unsigned IPL3 :1; /* CPU Interrupt Priority Level bit 3 */\r
- unsigned ACCSAT :1; /* Acc saturation mode */\r
- unsigned SATDW :1; /* Data space write saturation enable */\r
- unsigned SATB :1; /* Acc B saturation enable */\r
- unsigned SATA :1; /* Acc A saturation enable */\r
- unsigned DL :3; /* DO loop nesting level status */\r
- unsigned EDT :1; /* Early DO loop termination control */\r
- unsigned US :1; /* Signed/Unsigned mode */\r
- unsigned :3;\r
-} CORCONBITS;\r
-extern volatile CORCONBITS CORCONbits __attribute__((__sfr__));\r
-\r
-/* MODCON: Modulo Addressing Control Register */\r
-extern volatile unsigned int MODCON __attribute__((__sfr__));\r
-typedef struct tagMODCONBITS {\r
- unsigned XWM :4; /* X-RAGU/X-WAGU modulo addressing register select */\r
- unsigned YWM :4; /* Y-RAGU modulo addressing register select */\r
- unsigned BWM :4; /* Bit-reversed addressing register select */\r
- unsigned :2;\r
- unsigned YMODEN :1; /* Y-RAGU modulo addressing enable */\r
- unsigned XMODEN :1; /* X-RAGU/X-WAGU modulo addressing enable */\r
-} MODCONBITS;\r
-extern volatile MODCONBITS MODCONbits __attribute__((__sfr__));\r
-\r
-/* XMODSRT: X-RAGU/X-WAGU modulo buffer start address */\r
-extern volatile unsigned int XMODSRT __attribute__((__sfr__));\r
-\r
-/* XMODEND: X-RAGU/X-WAGU modulo buffer end address */\r
-extern volatile unsigned int XMODEND __attribute__((__sfr__));\r
-\r
-/* YMODSRT: Y-RAGU modulo buffer start address */\r
-extern volatile unsigned int YMODSRT __attribute__((__sfr__));\r
-\r
-/* YMODEND: Y-RAGU modulo buffer end address */\r
-extern volatile unsigned int YMODEND __attribute__((__sfr__));\r
-\r
-/* XBREV: X-WAGU Bit-reversed Addressing Control Register */\r
-extern volatile unsigned int XBREV __attribute__((__sfr__));\r
-typedef struct tagXBREVBITS {\r
- unsigned XB :15; /* Bit-reversed addressing register select */\r
- unsigned BREN :1; /* Bit-reversed addressing enable */\r
-} XBREVBITS;\r
-extern volatile XBREVBITS XBREVbits __attribute__((__sfr__));\r
-\r
-/* DISICNT: Disable Interrupt Cycle Count */\r
-extern volatile unsigned int DISICNT __attribute__((__sfr__));\r
-typedef struct tagDISICNTBITS {\r
- unsigned DISICNT:14;\r
- unsigned :2;\r
-} DISICNTBITS;\r
-extern volatile DISICNTBITS DISICNTbits __attribute__((__sfr__));\r
-\r
-\r
-/* ----------------------------------------- */\r
-/* Interrupt Controller register definitions */\r
-/* ----------------------------------------- */\r
-\r
-/* INTCON1: Interrupt Control Register 1 */\r
-extern volatile unsigned int INTCON1 __attribute__((__sfr__));\r
-typedef struct tagINTCON1BITS {\r
- unsigned :1;\r
- unsigned OSCFAIL:1;\r
- unsigned STKERR :1;\r
- unsigned ADDRERR:1;\r
- unsigned MATHERR:1;\r
- unsigned :3;\r
- unsigned COVTE :1;\r
- unsigned OVBTE :1;\r
- unsigned OVATE :1;\r
- unsigned :4;\r
- unsigned NSTDIS :1;\r
-} INTCON1BITS;\r
-extern volatile INTCON1BITS INTCON1bits __attribute__((__sfr__));\r
-\r
-/* INTCON2: Interrupt Control Register 2 */\r
-extern volatile unsigned int INTCON2 __attribute__((__sfr__));\r
-typedef struct tagINTCON2BITS {\r
- unsigned INT0EP :1;\r
- unsigned INT1EP :1;\r
- unsigned INT2EP :1;\r
- unsigned :11;\r
- unsigned DISI :1; \r
- unsigned ALTIVT :1;\r
-} INTCON2BITS;\r
-extern volatile INTCON2BITS INTCON2bits __attribute__((__sfr__));\r
-\r
-/* IFS0: Interrupt Flag Status Register 0 */\r
-extern volatile unsigned int IFS0 __attribute__((__sfr__));\r
-typedef struct tagIFS0BITS {\r
- unsigned INT0IF :1;\r
- unsigned IC1IF :1;\r
- unsigned OC1IF :1;\r
- unsigned T1IF :1;\r
- unsigned IC2IF :1;\r
- unsigned OC2IF :1;\r
- unsigned T2IF :1;\r
- unsigned T3IF :1;\r
- unsigned SPI1IF :1;\r
- unsigned U1RXIF :1;\r
- unsigned U1TXIF :1;\r
- unsigned ADIF :1;\r
- unsigned NVMIF :1;\r
- unsigned SI2CIF :1;\r
- unsigned MI2CIF :1;\r
- unsigned CNIF :1;\r
-} IFS0BITS;\r
-extern volatile IFS0BITS IFS0bits __attribute__((__sfr__));\r
-\r
-/* IFS1: Interrupt Flag Status Register 1 */\r
-extern volatile unsigned int IFS1 __attribute__((__sfr__));\r
-typedef struct tagIFS1BITS {\r
- unsigned INT1IF :1;\r
- unsigned IC7IF :1;\r
- unsigned IC8IF :1;\r
- unsigned :2;\r
- unsigned T4IF :1;\r
- unsigned T5IF :1;\r
- unsigned INT2IF :1;\r
- unsigned :3;\r
- unsigned C1IF :1;\r
- unsigned :4;\r
-} IFS1BITS;\r
-extern volatile IFS1BITS IFS1bits __attribute__((__sfr__));\r
-\r
-/* IFS2: Interrupt Flag Status Register 2 */\r
-extern volatile unsigned int IFS2 __attribute__((__sfr__));\r
-typedef struct tagIFS2BITS {\r
- unsigned :7;\r
- unsigned PWMIF :1;\r
- unsigned QEIIF :1;\r
- unsigned :2;\r
- unsigned FLTAIF :1;\r
- unsigned :4;\r
-} IFS2BITS;\r
-extern volatile IFS2BITS IFS2bits __attribute__((__sfr__));\r
-\r
-/* IEC0: Interrupt Enable Control Register 0 */\r
-extern volatile unsigned int IEC0 __attribute__((__sfr__));\r
-typedef struct tagIEC0BITS {\r
- unsigned INT0IE :1;\r
- unsigned IC1IE :1;\r
- unsigned OC1IE :1;\r
- unsigned T1IE :1;\r
- unsigned IC2IE :1;\r
- unsigned OC2IE :1;\r
- unsigned T2IE :1;\r
- unsigned T3IE :1;\r
- unsigned SPI1IE :1;\r
- unsigned U1RXIE :1;\r
- unsigned U1TXIE :1;\r
- unsigned ADIE :1;\r
- unsigned NVMIE :1;\r
- unsigned SI2CIE :1;\r
- unsigned MI2CIE :1;\r
- unsigned CNIE :1;\r
-} IEC0BITS;\r
-extern volatile IEC0BITS IEC0bits __attribute__((__sfr__));\r
-\r
-/* IEC1: Interrupt Enable Control Register 1 */\r
-extern volatile unsigned int IEC1 __attribute__((__sfr__));\r
-typedef struct tagIEC1BITS {\r
- unsigned INT1IE :1;\r
- unsigned IC7IE :1;\r
- unsigned IC8IE :1;\r
- unsigned :2;\r
- unsigned T4IE :1;\r
- unsigned T5IE :1;\r
- unsigned INT2IE :1;\r
- unsigned :3;\r
- unsigned C1IE :1;\r
- unsigned :4;\r
-} IEC1BITS;\r
-extern volatile IEC1BITS IEC1bits __attribute__((__sfr__));\r
-\r
-/* IEC2: Interrupt Enable Control Register 2 */\r
-extern volatile unsigned int IEC2 __attribute__((__sfr__));\r
-typedef struct tagIEC2BITS {\r
- unsigned :7;\r
- unsigned PWMIE :1;\r
- unsigned QEIIE :1;\r
- unsigned :2;\r
- unsigned FLTAIE :1;\r
- unsigned :4;\r
-} IEC2BITS;\r
-extern volatile IEC2BITS IEC2bits __attribute__((__sfr__));\r
-\r
-/* IPC0: Interrupt Priority Control Register 0 */\r
-extern volatile unsigned int IPC0 __attribute__((__sfr__));\r
-typedef struct tagIPC0BITS {\r
- unsigned INT0IP :3;\r
- unsigned :1;\r
- unsigned IC1IP :3;\r
- unsigned :1;\r
- unsigned OC1IP :3;\r
- unsigned :1;\r
- unsigned T1IP :3;\r
- unsigned :1;\r
-} IPC0BITS;\r
-extern volatile IPC0BITS IPC0bits __attribute__((__sfr__));\r
-\r
-/* IPC1: Interrupt Priority Control Register 1 */\r
-extern volatile unsigned int IPC1 __attribute__((__sfr__));\r
-typedef struct tagIPC1BITS {\r
- unsigned IC2IP :3;\r
- unsigned :1;\r
- unsigned OC2IP :3;\r
- unsigned :1;\r
- unsigned T2IP :3;\r
- unsigned :1;\r
- unsigned T3IP :3;\r
- unsigned :1;\r
-} IPC1BITS;\r
-extern volatile IPC1BITS IPC1bits __attribute__((__sfr__));\r
-\r
-/* IPC2: Interrupt Priority Control Register 2 */\r
-extern volatile unsigned int IPC2 __attribute__((__sfr__));\r
-typedef struct tagIPC2BITS {\r
- unsigned SPI1IP :3;\r
- unsigned :1;\r
- unsigned U1RXIP :3;\r
- unsigned :1;\r
- unsigned U1TXIP :3;\r
- unsigned :1;\r
- unsigned ADIP :3;\r
- unsigned :1;\r
-} IPC2BITS;\r
-extern volatile IPC2BITS IPC2bits __attribute__((__sfr__));\r
-\r
-/* IPC3: Interrupt Priority Control Register 3 */\r
-extern volatile unsigned int IPC3 __attribute__((__sfr__));\r
-typedef struct tagIPC3BITS {\r
- unsigned NVMIP :3;\r
- unsigned :1;\r
- unsigned SI2CIP :3;\r
- unsigned :1;\r
- unsigned MI2CIP :3;\r
- unsigned :1;\r
- unsigned CNIP :3;\r
- unsigned :1;\r
-} IPC3BITS;\r
-extern volatile IPC3BITS IPC3bits __attribute__((__sfr__));\r
-\r
-/* IPC4: Interrupt Priority Control Register 4 */\r
-extern volatile unsigned int IPC4 __attribute__((__sfr__));\r
-typedef struct tagIPC4BITS {\r
- unsigned INT1IP :3;\r
- unsigned :1;\r
- unsigned IC7IP :3;\r
- unsigned :1;\r
- unsigned IC8IP :3;\r
- unsigned :5;\r
-} IPC4BITS;\r
-extern volatile IPC4BITS IPC4bits __attribute__((__sfr__));\r
-\r
-/* IPC5: Interrupt Priority Control Register 5 */\r
-extern volatile unsigned int IPC5 __attribute__((__sfr__));\r
-typedef struct tagIPC5BITS {\r
- unsigned :4;\r
- unsigned T4IP :3;\r
- unsigned :1;\r
- unsigned T5IP :3;\r
- unsigned :1;\r
- unsigned INT2IP :3;\r
- unsigned :1;\r
-} IPC5BITS;\r
-extern volatile IPC5BITS IPC5bits __attribute__((__sfr__));\r
-\r
-/* IPC6: Interrupt Priority Control Register 6 */\r
-extern volatile unsigned int IPC6 __attribute__((__sfr__));\r
-typedef struct tagIPC6BITS {\r
- unsigned :12;\r
- unsigned C1IP :3;\r
- unsigned :1;\r
-} IPC6BITS;\r
-extern volatile IPC6BITS IPC6bits __attribute__((__sfr__));\r
-\r
-/* IPC9: Interrupt Priority Control Register 9 */\r
-extern volatile unsigned int IPC9 __attribute__((__sfr__));\r
-typedef struct tagIPC9BITS {\r
- unsigned :12;\r
- unsigned PWMIP :3;\r
- unsigned :1;\r
-} IPC9BITS;\r
-extern volatile IPC9BITS IPC9bits __attribute__((__sfr__));\r
-\r
-/* IPC10: Interrupt Priority Control Register 10 */\r
-extern volatile unsigned int IPC10 __attribute__((__sfr__));\r
-typedef struct tagIPC10BITS {\r
- unsigned QEIIP :3;\r
- unsigned :9;\r
- unsigned FLTAIP :3;\r
- unsigned :1;\r
-} IPC10BITS;\r
-extern volatile IPC10BITS IPC10bits __attribute__((__sfr__));\r
-\r
-/* ---------------------------------------------- */\r
-/* Input Change Notification register definitions */\r
-/* ---------------------------------------------- */\r
-\r
-/* CNEN1: Input Change Notification Interrupt Enable Register 1 */\r
-extern volatile unsigned int CNEN1 __attribute__((__sfr__));\r
-typedef struct tagCNEN1BITS {\r
- unsigned CN0IE :1;\r
- unsigned CN1IE :1;\r
- unsigned CN2IE :1;\r
- unsigned CN3IE :1;\r
- unsigned CN4IE :1;\r
- unsigned CN5IE :1;\r
- unsigned CN6IE :1;\r
- unsigned CN7IE :1;\r
- unsigned :8;\r
-} CNEN1BITS;\r
-extern volatile CNEN1BITS CNEN1bits __attribute__((__sfr__));\r
-\r
-/* CNPU1: Input Change Notification Pullup Enable Register 1 */\r
-extern volatile unsigned int CNPU1 __attribute__((__sfr__));\r
-typedef struct tagCNPU1BITS {\r
- unsigned CN0PUE :1;\r
- unsigned CN1PUE :1;\r
- unsigned CN2PUE :1;\r
- unsigned CN3PUE :1;\r
- unsigned CN4PUE :1;\r
- unsigned CN5PUE :1;\r
- unsigned CN6PUE :1;\r
- unsigned CN7PUE :1;\r
- unsigned :8;\r
-} CNPU1BITS;\r
-extern volatile CNPU1BITS CNPU1bits __attribute__((__sfr__));\r
-\r
-\r
-/* --------------------------- */\r
-/* Timer1 register definitions */\r
-/* --------------------------- */\r
-\r
-/* Generic structure for Timer 1 Control Register */\r
-typedef struct tagTCON_16BIT {\r
- unsigned :1;\r
- unsigned TCS :1;\r
- unsigned TSYNC :1;\r
- unsigned :1;\r
- unsigned TCKPS :2;\r
- unsigned TGATE :1;\r
- unsigned :6;\r
- unsigned TSIDL :1;\r
- unsigned :1;\r
- unsigned TON :1;\r
-} TCON_16BIT;\r
-\r
-/* TMR1: Timer 1 Count Register */\r
-extern volatile unsigned int TMR1 __attribute__((__sfr__));\r
-\r
-/* PR1: Timer 1 Period Register */\r
-extern volatile unsigned int PR1 __attribute__((__sfr__));\r
-\r
-/* T1CON: Timer 1 Control Register */\r
-extern volatile unsigned int T1CON __attribute__((__sfr__));\r
-extern volatile TCON_16BIT T1CONbits __attribute__((__sfr__));\r
-\r
-/* ----------------------------- */\r
-/* Timer2/3 register definitions */\r
-/* ----------------------------- */\r
-\r
-/* Generic structure for Timer 2 and Timer 4 Control Registers */\r
-typedef struct tagTCON_EVEN {\r
- unsigned :1;\r
- unsigned TCS :1;\r
- unsigned :1;\r
- unsigned T32 :1;\r
- unsigned TCKPS :2;\r
- unsigned TGATE :1;\r
- unsigned :6;\r
- unsigned TSIDL :1;\r
- unsigned :1;\r
- unsigned TON :1;\r
-} TCON_EVEN;\r
-\r
-/* Generic structure for Timer 3 and Timer 5 Control Registers */\r
-typedef struct tagTCON_ODD {\r
- unsigned :1;\r
- unsigned TCS :1;\r
- unsigned :2;\r
- unsigned TCKPS :2;\r
- unsigned TGATE :1;\r
- unsigned :6;\r
- unsigned TSIDL :1;\r
- unsigned :1;\r
- unsigned TON :1;\r
-} TCON_ODD;\r
-\r
-/* TMR2: Timer 2 Count Register */\r
-extern volatile unsigned int TMR2 __attribute__((__sfr__));\r
-\r
-/* TMR3HLD: Timer 3 Holding Register */\r
-extern volatile unsigned int TMR3HLD __attribute__((__sfr__));\r
-\r
-/* TMR3: Timer 3 Count Register */\r
-extern volatile unsigned int TMR3 __attribute__((__sfr__));\r
-\r
-/* PR2: Timer 2 Period Register */\r
-extern volatile unsigned int PR2 __attribute__((__sfr__));\r
-\r
-/* PR3: Timer 3 Period Register */\r
-extern volatile unsigned int PR3 __attribute__((__sfr__));\r
-\r
-/* T2CON: Timer 2 Control Register */\r
-extern volatile unsigned int T2CON __attribute__((__sfr__));\r
-extern volatile TCON_EVEN T2CONbits __attribute__((__sfr__));\r
-\r
-/* T3CON: Timer 3 Control Register */\r
-extern volatile unsigned int T3CON __attribute__((__sfr__));\r
-extern volatile TCON_ODD T3CONbits __attribute__((__sfr__));\r
-\r
-/* ----------------------------- */\r
-/* Timer4/5 register definitions */\r
-/* ----------------------------- */\r
-\r
-/* TMR4: Timer 4 Count Register */\r
-extern volatile unsigned int TMR4 __attribute__((__sfr__));\r
-\r
-/* TMR5HLD: Timer 5 Holding Register */\r
-extern volatile unsigned int TMR5HLD __attribute__((__sfr__));\r
-\r
-/* TMR5: Timer 5 Count Register */\r
-extern volatile unsigned int TMR5 __attribute__((__sfr__));\r
-\r
-/* PR4: Timer 4 Period Register */\r
-extern volatile unsigned int PR4 __attribute__((__sfr__));\r
-\r
-/* PR5: Timer 5 Period Register */\r
-extern volatile unsigned int PR5 __attribute__((__sfr__));\r
-\r
-/* T4CON: Timer 4 Control Register */\r
-extern volatile unsigned int T4CON __attribute__((__sfr__));\r
-extern volatile TCON_EVEN T4CONbits __attribute__((__sfr__));\r
-\r
-/* T5CON: Timer 5 Control Register */\r
-extern volatile unsigned int T5CON __attribute__((__sfr__));\r
-extern volatile TCON_ODD T5CONbits __attribute__((__sfr__));\r
-\r
-/* ------------------------------------------------- */\r
-/* Quadrature Encoder Interface register definitions */\r
-/* ------------------------------------------------- */\r
-\r
-/* QEICON: QEI Control Register */\r
-extern volatile unsigned int QEICON __attribute__((__sfr__));\r
-typedef struct tagQEICONBITS {\r
- unsigned UPDN_SRC:1;\r
- unsigned TQCS :1;\r
- unsigned POSRES :1;\r
- unsigned TQCKPS :2;\r
- unsigned TQGATE :1;\r
- unsigned PCDOUT :1;\r
- unsigned SWPAB :1;\r
- unsigned QEIM :3;\r
- unsigned UPDN :1;\r
- unsigned INDX :1;\r
- unsigned QEISIDL:1;\r
- unsigned :1;\r
- unsigned CNTERR :1;\r
-} QEICONBITS;\r
-extern volatile QEICONBITS QEICONbits __attribute__((__sfr__));\r
-\r
-/* DFLTCON: Digital Filter Control Register */\r
-extern volatile unsigned int DFLTCON __attribute__((__sfr__));\r
-typedef struct tagDFLTCONBITS {\r
- unsigned :4;\r
- unsigned QECK :3;\r
- unsigned QEOUT :1;\r
- unsigned CEID :1;\r
- unsigned IMV :2;\r
- unsigned :5;\r
-} DFLTCONBITS;\r
-extern volatile DFLTCONBITS DFLTCONbits __attribute__((__sfr__));\r
-\r
-/* POSCNT: Position Counter Register */\r
-extern volatile unsigned int POSCNT __attribute__((__sfr__));\r
-\r
-/* MAXCNT: Maximum Count Register */\r
-extern volatile unsigned int MAXCNT __attribute__((__sfr__));\r
-\r
-/* ---------------------------------- */\r
-/* Input Capture register definitions */\r
-/* ---------------------------------- */\r
-\r
-/* Generic structure of entire SFR area for each Input Capture module */\r
-typedef struct tagIC {\r
- unsigned int icxbuf;\r
- unsigned int icxcon;\r
-} IC, *PIC;\r
-\r
-/* SFR blocks for each Input Capture module */\r
-extern volatile IC IC1 __attribute__((__sfr__));\r
-extern volatile IC IC2 __attribute__((__sfr__));\r
-extern volatile IC IC7 __attribute__((__sfr__));\r
-extern volatile IC IC8 __attribute__((__sfr__));\r
-\r
-/* Generic structure for Input Capture Control Registers */\r
-typedef struct tagICxCONBITS {\r
- unsigned ICM :3;\r
- unsigned ICBNE :1;\r
- unsigned ICOV :1;\r
- unsigned ICI :2;\r
- unsigned ICTMR :1;\r
- unsigned :5;\r
- unsigned ICSIDL :1;\r
- unsigned :2;\r
-} ICxCONBITS;\r
-\r
-/* IC1BUF: Input Capture 1 Buffer */\r
-extern volatile unsigned int IC1BUF __attribute__((__sfr__));\r
-\r
-/* IC1CON: Input Capture 1 Control Register */\r
-extern volatile unsigned int IC1CON __attribute__((__sfr__));\r
-extern volatile ICxCONBITS IC1CONbits __attribute__((__sfr__));\r
-\r
-/* IC2BUF: Input Capture 2 Buffer */\r
-extern volatile unsigned int IC2BUF __attribute__((__sfr__));\r
-\r
-/* IC2CON: Input Capture 2 Control Register */\r
-extern volatile unsigned int IC2CON __attribute__((__sfr__));\r
-extern volatile ICxCONBITS IC2CONbits __attribute__((__sfr__));\r
-\r
-/* IC7BUF: Input Capture 7 Buffer */\r
-extern volatile unsigned int IC7BUF __attribute__((__sfr__));\r
-\r
-/* IC7CON: Input Capture 7 Control Register */\r
-extern volatile unsigned int IC7CON __attribute__((__sfr__));\r
-extern volatile ICxCONBITS IC7CONbits __attribute__((__sfr__));\r
-\r
-/* IC8BUF: Input Capture 8 Buffer */\r
-extern volatile unsigned int IC8BUF __attribute__((__sfr__));\r
-\r
-/* IC8CON: Input Capture 8 Control Register */\r
-extern volatile unsigned int IC8CON __attribute__((__sfr__));\r
-extern volatile ICxCONBITS IC8CONbits __attribute__((__sfr__));\r
-\r
-\r
-/* --------------------------------------- */\r
-/* Output Compare/PWM register definitions */\r
-/* --------------------------------------- */\r
-\r
-/* Generic structure of entire SFR area for each Output Compare module */\r
-typedef struct tagOC {\r
- unsigned int ocxrs;\r
- unsigned int ocxr;\r
- unsigned int ocxcon;\r
-} OC, *POC;\r
-\r
-/* SFR blocks for each Output Compare module */\r
-extern volatile OC OC1 __attribute__((__sfr__));\r
-extern volatile OC OC2 __attribute__((__sfr__));\r
-\r
-/* Generic structure for Output Compare Control Registers */\r
-typedef struct tagOCxCONBITS {\r
- unsigned OCM :3;\r
- unsigned OCTSEL :1;\r
- unsigned OCFLT :1;\r
- unsigned :8;\r
- unsigned OCSIDL :1;\r
- unsigned :2;\r
-} OCxCONBITS;\r
-\r
-/* OC1RS: Output Compare 1 Secondary Register */\r
-extern volatile unsigned int OC1RS __attribute__((__sfr__));\r
-\r
-/* OC1R: Output Compare 1 Main Register */\r
-extern volatile unsigned int OC1R __attribute__((__sfr__));\r
-\r
-/* OC1CON: Output Compare 1 Control Register */\r
-extern volatile unsigned int OC1CON __attribute__((__sfr__));\r
-extern volatile OCxCONBITS OC1CONbits __attribute__((__sfr__));\r
-\r
-/* OC2RS: Output Compare 2 Secondary Register */\r
-extern volatile unsigned int OC2RS __attribute__((__sfr__));\r
-\r
-/* OC2R: Output Compare 2 Main Register */\r
-extern volatile unsigned int OC2R __attribute__((__sfr__));\r
-\r
-/* OC2CON: Output Compare 2 Control Register */\r
-extern volatile unsigned int OC2CON __attribute__((__sfr__));\r
-extern volatile OCxCONBITS OC2CONbits __attribute__((__sfr__));\r
-\r
-\r
-/* -------------------------------------- */\r
-/* Motor Control PWM register definitions */\r
-/* -------------------------------------- */\r
-\r
-/* PTCON: PWM Timerbase Control Register */\r
-extern volatile unsigned int PTCON __attribute__((__sfr__));\r
-typedef struct tagPTCONBITS {\r
- unsigned PTMOD :2;\r
- unsigned PTCKPS :2;\r
- unsigned PTOPS :4;\r
- unsigned :5;\r
- unsigned PTSIDL :1;\r
- unsigned :1;\r
- unsigned PTEN :1;\r
-} PTCONBITS;\r
-extern volatile PTCONBITS PTCONbits __attribute__((__sfr__));\r
-\r
-/* PTMR: PWM Timebase Count Register */\r
-extern volatile unsigned int PTMR __attribute__((__sfr__));\r
-typedef struct tagPTMRBITS {\r
- unsigned PTMR :15;\r
- unsigned PTDIR :1;\r
-} PTMRBITS;\r
-extern volatile PTMRBITS PTMRbits __attribute__((__sfr__));\r
-\r
-/* PTPER: PWM Timebase Period Register */\r
-extern volatile unsigned int PTPER __attribute__((__sfr__));\r
-typedef struct tagPTPERBITS {\r
- unsigned PTPER :15;\r
- unsigned :1;\r
-} PTPERBITS;\r
-extern volatile PTPERBITS PTPERbits __attribute__((__sfr__));\r
-\r
-/* SEVTCMP: Special Event Compare Count Register */\r
-extern volatile unsigned int SEVTCMP __attribute__((__sfr__));\r
-typedef struct tagSEVTCMPBITS {\r
- unsigned SEVTCMP:15;\r
- unsigned SEVTDIR:1;\r
-} SEVTCMPBITS;\r
-extern volatile SEVTCMPBITS SEVTCMPbits __attribute__((__sfr__));\r
-\r
-/* PWMCON1: PWM Control Register 1 */\r
-extern volatile unsigned int PWMCON1 __attribute__((__sfr__));\r
-typedef struct tagPWMCON1BITS {\r
- unsigned PEN1L :1;\r
- unsigned PEN2L :1;\r
- unsigned PEN3L :1;\r
- unsigned :1;\r
- unsigned PEN1H :1;\r
- unsigned PEN2H :1;\r
- unsigned PEN3H :1;\r
- unsigned :1;\r
- unsigned PMOD1 :1;\r
- unsigned PMOD2 :1;\r
- unsigned PMOD3 :1;\r
- unsigned :5;\r
-} PWMCON1BITS;\r
-extern volatile PWMCON1BITS PWMCON1bits __attribute__((__sfr__));\r
-\r
-/* PWMCON2: PWM Control Register 2 */\r
-extern volatile unsigned int PWMCON2 __attribute__((__sfr__));\r
-typedef struct tagPWMCON2BITS {\r
- unsigned UDIS :1;\r
- unsigned OSYNC :1;\r
- unsigned IUE :1; \r
- unsigned :5;\r
- unsigned SEVOPS :4;\r
- unsigned :4;\r
-} PWMCON2BITS;\r
-extern volatile PWMCON2BITS PWMCON2bits __attribute__((__sfr__));\r
-\r
-/* DTCON1: PWM Dead Time Control Register 1 */\r
-extern volatile unsigned int DTCON1 __attribute__((__sfr__));\r
-typedef struct tagDTCON1BITS {\r
- unsigned DTA :6;\r
- unsigned DTAPS :2;\r
- unsigned :8;\r
-} DTCON1BITS;\r
-extern volatile DTCON1BITS DTCON1bits __attribute__((__sfr__));\r
-\r
-/* FLTACON: PWM Fault Input A Control Register */ \r
-extern volatile unsigned int FLTACON __attribute__((__sfr__));\r
-typedef struct tagFLTACONBITS {\r
- unsigned FAEN1 :1;\r
- unsigned FAEN2 :1;\r
- unsigned FAEN3 :1;\r
- unsigned :4;\r
- unsigned FLTAM :1;\r
- unsigned FAOV1L :1;\r
- unsigned FAOV1H :1;\r
- unsigned FAOV2L :1;\r
- unsigned FAOV2H :1;\r
- unsigned FAOV3L :1;\r
- unsigned FAOV3H :1;\r
- unsigned :2;\r
-} FLTACONBITS;\r
-extern volatile FLTACONBITS FLTACONbits __attribute__((__sfr__));\r
-\r
-/* OVDCON: PWM Override Control Register */\r
-extern volatile unsigned int OVDCON __attribute__((__sfr__));\r
-typedef struct tagOVDCONBITS {\r
- unsigned POUT1L :1;\r
- unsigned POUT1H :1;\r
- unsigned POUT2L :1;\r
- unsigned POUT2H :1;\r
- unsigned POUT3L :1;\r
- unsigned POUT3H :1;\r
- unsigned :2;\r
- unsigned POVD1L :1;\r
- unsigned POVD1H :1;\r
- unsigned POVD2L :1;\r
- unsigned POVD2H :1;\r
- unsigned POVD3L :1;\r
- unsigned POVD3H :1;\r
- unsigned :2;\r
-} OVDCONBITS;\r
-extern volatile OVDCONBITS OVDCONbits __attribute__((__sfr__));\r
-\r
-/* PDC1: PWM Duty Cycle Register 1 */\r
-extern volatile unsigned int PDC1 __attribute__((__sfr__));\r
-\r
-/* PDC2: PWM Duty Cycle Register 2 */\r
-extern volatile unsigned int PDC2 __attribute__((__sfr__));\r
-\r
-/* PDC3: PWM Duty Cycle Register 3 */\r
-extern volatile unsigned int PDC3 __attribute__((__sfr__));\r
-\r
-\r
-/* ------------------------ */\r
-/* I2C register definitions */\r
-/* ------------------------ */\r
-\r
-/* I2CRCV: I2C Receive Register */\r
-extern volatile unsigned char I2CRCV __attribute__((__sfr__));\r
-typedef struct tagI2CRCVBITS {\r
- unsigned I2CRCV0:1;\r
- unsigned I2CRCV1:1;\r
- unsigned I2CRCV2:1;\r
- unsigned I2CRCV3:1;\r
- unsigned I2CRCV4:1;\r
- unsigned I2CRCV5:1;\r
- unsigned I2CRCV6:1;\r
- unsigned I2CRCV7:1;\r
-} I2CRCVBITS;\r
-extern volatile I2CRCVBITS I2CRCVbits __attribute__((__sfr__));\r
-\r
-/* I2CTRN: I2C Transmit Register */\r
-extern volatile unsigned char I2CTRN __attribute__((__sfr__));\r
-typedef struct tagI2CTRNBITS {\r
- unsigned I2CTRN0:1;\r
- unsigned I2CTRN1:1;\r
- unsigned I2CTRN2:1;\r
- unsigned I2CTRN3:1;\r
- unsigned I2CTRN4:1;\r
- unsigned I2CTRN5:1;\r
- unsigned I2CTRN6:1;\r
- unsigned I2CTRN7:1;\r
-} I2CTRNBITS;\r
-extern volatile I2CTRNBITS I2CTRNbits __attribute__((__sfr__));\r
-\r
-/* I2CBRG: I2C Baud Rate Generator Register */\r
-extern volatile unsigned int I2CBRG __attribute__((__sfr__));\r
-typedef struct tagI2CBRGBITS {\r
- unsigned I2CBRG :9;\r
- unsigned :7;\r
-} I2CBRGBITS;\r
-extern volatile I2CBRGBITS I2CBRGbits __attribute__((__sfr__));\r
-\r
-/* I2CCON: I2C Control Register */\r
-extern volatile unsigned int I2CCON __attribute__((__sfr__));\r
-typedef struct tagI2CCONBITS {\r
- unsigned SEN :1;\r
- unsigned RSEN :1;\r
- unsigned PEN :1;\r
- unsigned RCEN :1;\r
- unsigned ACKEN :1;\r
- unsigned ACKDT :1;\r
- unsigned STREN :1;\r
- unsigned GCEN :1;\r
- unsigned SMEN :1;\r
- unsigned DISSLW :1;\r
- unsigned A10M :1;\r
- unsigned IPMIEN :1;\r
- unsigned SCLREL :1;\r
- unsigned I2CSIDL:1;\r
- unsigned :1;\r
- unsigned I2CEN :1;\r
-} I2CCONBITS;\r
-extern volatile I2CCONBITS I2CCONbits __attribute__((__sfr__));\r
-\r
-/* I2CSTAT: I2C Status Register */\r
-extern volatile unsigned int I2CSTAT __attribute__((__sfr__));\r
-typedef struct tagI2CSTATBITS {\r
- unsigned TBF :1;\r
- unsigned RBF :1;\r
- unsigned R_W :1;\r
- unsigned S :1;\r
- unsigned P :1;\r
- unsigned D_A :1;\r
- unsigned I2COV :1;\r
- unsigned IWCOL :1;\r
- unsigned ADD10 :1;\r
- unsigned GCSTAT :1;\r
- unsigned BCL :1;\r
- unsigned :3;\r
- unsigned TRSTAT :1;\r
- unsigned ACKSTAT:1;\r
-} I2CSTATBITS;\r
-extern volatile I2CSTATBITS I2CSTATbits __attribute__((__sfr__));\r
-\r
-/* I2CADD: I2C Address Register */\r
-extern volatile unsigned int I2CADD __attribute__((__sfr__));\r
-typedef struct tagI2CADDBITS {\r
- unsigned I2CADD :10;\r
- unsigned :6;\r
-} I2CADDBITS;\r
-extern volatile I2CADDBITS I2CADDbits __attribute__((__sfr__));\r
-\r
-\r
-/* -------------------------- */\r
-/* UART1 register definitions */\r
-/* -------------------------- */\r
-\r
-/* Generic structure of entire SFR area for each UART module */\r
-typedef struct tagUART {\r
- unsigned int uxmode;\r
- unsigned int uxsta;\r
- unsigned int uxtxreg;\r
- unsigned int uxrxreg;\r
- unsigned int uxbrg;\r
-} UART, *PUART;\r
-\r
-/* SFR blocks for each UART module */\r
-extern volatile UART UART1 __attribute__((__sfr__));\r
-\r
-/* Generic structure for UART Mode Registers */\r
-typedef struct tagUxMODEBITS {\r
- unsigned STSEL :1;\r
- unsigned PDSEL :2;\r
- unsigned :2;\r
- unsigned ABAUD :1;\r
- unsigned LPBACK :1;\r
- unsigned WAKE :1;\r
- unsigned :2;\r
- unsigned ALTIO :1;\r
- unsigned :2;\r
- unsigned USIDL :1;\r
- unsigned :1;\r
- unsigned UARTEN :1;\r
-} UxMODEBITS;\r
-\r
-/* Generic structure for UART Status and Control Registers */\r
-typedef struct tagUxSTABITS {\r
- unsigned URXDA :1;\r
- unsigned OERR :1;\r
- unsigned FERR :1;\r
- unsigned PERR :1;\r
- unsigned RIDLE :1;\r
- unsigned ADDEN :1;\r
- unsigned URXISEL:2;\r
- unsigned TRMT :1;\r
- unsigned UTXBF :1;\r
- unsigned UTXEN :1;\r
- unsigned UTXBRK :1;\r
- unsigned :3;\r
- unsigned UTXISEL:1;\r
-} UxSTABITS; \r
-\r
-/* Generic structure for UART Transmit Registers */\r
-typedef struct tagUxTXREGBITS {\r
- unsigned UTXREG0:1;\r
- unsigned UTXREG1:1;\r
- unsigned UTXREG2:1;\r
- unsigned UTXREG3:1;\r
- unsigned UTXREG4:1;\r
- unsigned UTXREG5:1;\r
- unsigned UTXREG6:1;\r
- unsigned UTXREG7:1;\r
- unsigned UTX8 :1;\r
- unsigned :7;\r
-} UxTXREGBITS;\r
-\r
-/* Generic structure for UART Receive Registers */\r
-typedef struct tagUxRXREGBITS {\r
- unsigned URXREG0:1;\r
- unsigned URXREG1:1;\r
- unsigned URXREG2:1;\r
- unsigned URXREG3:1;\r
- unsigned URXREG4:1;\r
- unsigned URXREG5:1;\r
- unsigned URXREG6:1;\r
- unsigned URXREG7:1;\r
- unsigned URX8 :1;\r
- unsigned :7;\r
-} UxRXREGBITS;\r
-\r
-/* U1MODE: UART1 Mode Regsiter */\r
-extern volatile unsigned int U1MODE __attribute__((__sfr__));\r
-extern volatile UxMODEBITS U1MODEbits __attribute__((__sfr__));\r
-\r
-/* U1STA: UART1 Status and Control Register */\r
-extern volatile unsigned int U1STA __attribute__((__sfr__));\r
-extern volatile UxSTABITS U1STAbits __attribute__((__sfr__));\r
-\r
-/* U1TXREG: UART1 Transmit Register */\r
-extern volatile unsigned int U1TXREG __attribute__((__sfr__));\r
-extern volatile UxTXREGBITS U1TXREGbits __attribute__((__sfr__));\r
-\r
-/* U1RXREG: UART1 Receive Register */\r
-extern volatile unsigned int U1RXREG __attribute__((__sfr__));\r
-extern volatile UxRXREGBITS U1RXREGbits __attribute__((__sfr__)); \r
-\r
-/* U1BRG: UART1 Baud Rate Generator Register */\r
-extern volatile unsigned int U1BRG __attribute__((__sfr__));\r
-\r
-\r
-/* ------------------------- */\r
-/* SPI1 register definitions */\r
-/* ------------------------- */\r
-\r
-/* Generic structure of entire SFR area for each SPI module */\r
-typedef struct tagSPI {\r
- unsigned int spixstat;\r
- unsigned int spixcon;\r
- unsigned int spixbuf;\r
-} SPI, *PSPI;\r
-\r
-/* SFR blocks for each SPI module */\r
-extern volatile SPI SPI1 __attribute__((__sfr__));\r
-\r
-/* Generic structure for SPI Status Registers */\r
-typedef struct tagSPIxSTATBITS {\r
- unsigned SPIRBF :1;\r
- unsigned SPITBF :1;\r
- unsigned :4;\r
- unsigned SPIROV :1;\r
- unsigned :6;\r
- unsigned SPISIDL:1;\r
- unsigned :1;\r
- unsigned SPIEN :1;\r
-} SPIxSTATBITS;\r
-\r
-/* Generic structure for SPI Control Registers */\r
-typedef struct tagSPIxCONBITS {\r
- unsigned PPRE :2;\r
- unsigned SPRE :3;\r
- unsigned MSTEN :1;\r
- unsigned CKP :1;\r
- unsigned SSEN :1;\r
- unsigned CKE :1;\r
- unsigned SMP :1;\r
- unsigned MODE16 :1;\r
- unsigned DISSDO :1;\r
- unsigned :1;\r
- unsigned SPIFSD:1;\r
- unsigned FRMEN :1;\r
- unsigned :1;\r
-} SPIxCONBITS;\r
-\r
-/* SPI1STAT: SPI1 Status Register */\r
-extern volatile unsigned int SPI1STAT __attribute__((__sfr__));\r
-extern volatile SPIxSTATBITS SPI1STATbits __attribute__((__sfr__));\r
-\r
-/* SPI1CON: SPI1 Control Register */\r
-extern volatile unsigned int SPI1CON __attribute__((__sfr__));\r
-extern volatile SPIxCONBITS SPI1CONbits __attribute__((__sfr__));\r
-\r
-/* SPI1BUF: SPI1 Buffer */\r
-extern volatile unsigned int SPI1BUF __attribute__((__sfr__));\r
-\r
-\r
-/* ------------------------------------------------------------------ */\r
-/* 10-bit (500 ksps) Analog-to-Digital Converter register definitions */\r
-/* ------------------------------------------------------------------ */\r
-\r
-/* ADC Buffers 0-F */\r
-extern volatile unsigned int ADCBUF0 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUF1 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUF2 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUF3 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUF4 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUF5 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUF6 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUF7 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUF8 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUF9 __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUFA __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUFB __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUFC __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUFD __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUFE __attribute__((__sfr__));\r
-extern volatile unsigned int ADCBUFF __attribute__((__sfr__));\r
-\r
-/* ADCON1: ADC Control Register 1 */\r
-extern volatile unsigned int ADCON1 __attribute__((__sfr__));\r
-typedef struct tagADCON1BITS {\r
- unsigned DONE :1;\r
- unsigned SAMP :1;\r
- unsigned ASAM :1;\r
- unsigned SIMSAM :1;\r
- unsigned :1;\r
- unsigned SSRC :3;\r
- unsigned FORM :2;\r
- unsigned :3;\r
- unsigned ADSIDL :1;\r
- unsigned :1;\r
- unsigned ADON :1;\r
-} ADCON1BITS;\r
-extern volatile ADCON1BITS ADCON1bits __attribute__((__sfr__));\r
-\r
-/* ADCON2: ADC Control Register 2 */\r
-extern volatile unsigned int ADCON2 __attribute__((__sfr__));\r
-typedef struct tagADCON2BITS {\r
- unsigned ALTS :1;\r
- unsigned BUFM :1;\r
- unsigned SMPI :4;\r
- unsigned :1;\r
- unsigned BUFS :1;\r
- unsigned CHPS :2;\r
- unsigned CSCNA :1;\r
- unsigned :2;\r
- unsigned VCFG :3;\r
-} ADCON2BITS;\r
-extern volatile ADCON2BITS ADCON2bits __attribute__((__sfr__));\r
-\r
-/* ADCON3: ADC Control Register 3 */\r
-extern volatile unsigned int ADCON3 __attribute__((__sfr__));\r
-typedef struct tagADCON3BITS {\r
- unsigned ADCS :6;\r
- unsigned :1;\r
- unsigned ADRC :1;\r
- unsigned SAMC :5;\r
- unsigned :3;\r
-} ADCON3BITS;\r
-extern volatile ADCON3BITS ADCON3bits __attribute__((__sfr__));\r
-\r
-/* ADCHS: ADC Input Channel Select Register */\r
-extern volatile unsigned int ADCHS __attribute__((__sfr__));\r
-typedef struct tagADCHSBITS {\r
- unsigned CH0SA :4;\r
- unsigned CH0NA :1;\r
- unsigned CH123SA:1;\r
- unsigned CH123NA:2;\r
- unsigned CH0SB :4;\r
- unsigned CH0NB :1;\r
- unsigned CH123SB:1;\r
- unsigned CH123NB:2;\r
-} ADCHSBITS;\r
-extern volatile ADCHSBITS ADCHSbits __attribute__((__sfr__));\r
-\r
-/* ADPCFG: ADC Port Configuration Register */\r
-extern volatile unsigned int ADPCFG __attribute__((__sfr__));\r
-typedef struct tagADPCFGBITS {\r
- unsigned PCFG0 :1;\r
- unsigned PCFG1 :1;\r
- unsigned PCFG2 :1;\r
- unsigned PCFG3 :1;\r
- unsigned PCFG4 :1;\r
- unsigned PCFG5 :1;\r
- unsigned :10;\r
-} ADPCFGBITS;\r
-extern volatile ADPCFGBITS ADPCFGbits __attribute__((__sfr__));\r
-\r
-/* ADCSSL: ADC Input Scan Select Register */\r
-extern volatile unsigned int ADCSSL __attribute__((__sfr__));\r
-typedef struct tagADCSSLBITS {\r
- unsigned CSSL0 :1;\r
- unsigned CSSL1 :1;\r
- unsigned CSSL2 :1;\r
- unsigned CSSL3 :1;\r
- unsigned CSSL4 :1;\r
- unsigned CSSL5 :1;\r
- unsigned :10;\r
-} ADCSSLBITS;\r
-extern volatile ADCSSLBITS ADCSSLbits __attribute__((__sfr__));\r
-\r
-\r
-/* ------------------------------ */\r
-/* I/O Ports register definitions */\r
-/* ------------------------------ */\r
-\r
-/* TRISB: Port B Direction Control Register */\r
-extern volatile unsigned int TRISB __attribute__((__sfr__));\r
-typedef struct tagTRISBBITS {\r
- unsigned TRISB0 :1;\r
- unsigned TRISB1 :1;\r
- unsigned TRISB2 :1;\r
- unsigned TRISB3 :1;\r
- unsigned TRISB4 :1;\r
- unsigned TRISB5 :1;\r
- unsigned :10;\r
-} TRISBBITS;\r
-extern volatile TRISBBITS TRISBbits __attribute__((__sfr__));\r
-\r
-/* PORTB: Port B Pin Register */\r
-extern volatile unsigned int PORTB __attribute__((__sfr__));\r
-typedef struct tagPORTBBITS {\r
- unsigned RB0 :1;\r
- unsigned RB1 :1;\r
- unsigned RB2 :1;\r
- unsigned RB3 :1;\r
- unsigned RB4 :1;\r
- unsigned RB5 :1;\r
- unsigned :10;\r
-} PORTBBITS;\r
-extern volatile PORTBBITS PORTBbits __attribute__((__sfr__));\r
-\r
-/* LATB: Port B Latch Register */\r
-extern volatile unsigned int LATB __attribute__((__sfr__));\r
-typedef struct tagLATBBITS {\r
- unsigned LATB0 :1;\r
- unsigned LATB1 :1;\r
- unsigned LATB2 :1;\r
- unsigned LATB3 :1;\r
- unsigned LATB4 :1;\r
- unsigned LATB5 :1;\r
- unsigned :10;\r
-} LATBBITS;\r
-extern volatile LATBBITS LATBbits __attribute__((__sfr__));\r
-\r
-/* TRISC: Port C Direction Control Register */\r
-extern volatile unsigned int TRISC __attribute__((__sfr__));\r
-typedef struct tagTRISCBITS {\r
- unsigned :13;\r
- unsigned TRISC13:1;\r
- unsigned TRISC14:1;\r
- unsigned TRISC15:1;\r
-} TRISCBITS;\r
-extern volatile TRISCBITS TRISCbits __attribute__((__sfr__));\r
-\r
-/* PORTC: Port C Pin Register */\r
-extern volatile unsigned int PORTC __attribute__((__sfr__));\r
-typedef struct tagPORTCBITS {\r
- unsigned :13;\r
- unsigned RC13 :1;\r
- unsigned RC14 :1;\r
- unsigned RC15 :1;\r
-} PORTCBITS;\r
-extern volatile PORTCBITS PORTCbits __attribute__((__sfr__));\r
-\r
-/* LATC: Port C Latch Register */\r
-extern volatile unsigned int LATC __attribute__((__sfr__));\r
-typedef struct tagLATCBITS {\r
- unsigned :13;\r
- unsigned LATC13 :1;\r
- unsigned LATC14 :1;\r
- unsigned LATC15 :1;\r
-} LATCBITS;\r
-extern volatile LATCBITS LATCbits __attribute__((__sfr__));\r
-\r
-/* TRISD: Port D Direction Control Register */\r
-extern volatile unsigned int TRISD __attribute__((__sfr__));\r
-typedef struct tagTRISDBITS {\r
- unsigned TRISD0 :1;\r
- unsigned TRISD1 :1;\r
- unsigned :14;\r
-} TRISDBITS;\r
-extern volatile TRISDBITS TRISDbits __attribute__((__sfr__));\r
-\r
-/* PORTD: Port D Pin Register */\r
-extern volatile unsigned int PORTD __attribute__((__sfr__));\r
-typedef struct tagPORTDBITS {\r
- unsigned RD0 :1;\r
- unsigned RD1 :1;\r
- unsigned :14;\r
-} PORTDBITS;\r
-extern volatile PORTDBITS PORTDbits __attribute__((__sfr__));\r
-\r
-/* LATD: Port D Latch Register */\r
-extern volatile unsigned int LATD __attribute__((__sfr__));\r
-typedef struct tagLATDBITS {\r
- unsigned LATD0 :1;\r
- unsigned LATD1 :1;\r
- unsigned :14;\r
-} LATDBITS;\r
-extern volatile LATDBITS LATDbits __attribute__((__sfr__));\r
-\r
-/* TRISE: Port E Direction Control Register */\r
-extern volatile unsigned int TRISE __attribute__((__sfr__));\r
-typedef struct tagTRISEBITS {\r
- unsigned TRISE0 :1;\r
- unsigned TRISE1 :1;\r
- unsigned TRISE2 :1;\r
- unsigned TRISE3 :1;\r
- unsigned TRISE4 :1;\r
- unsigned TRISE5 :1;\r
- unsigned :2;\r
- unsigned TRISE8 :1;\r
- unsigned :7;\r
-} TRISEBITS;\r
-extern volatile TRISEBITS TRISEbits __attribute__((__sfr__));\r
-\r
-/* PORTE: Port E Pin Register */\r
-extern volatile unsigned int PORTE __attribute__((__sfr__));\r
-typedef struct tagPORTEBITS {\r
- unsigned RE0 :1;\r
- unsigned RE1 :1;\r
- unsigned RE2 :1;\r
- unsigned RE3 :1;\r
- unsigned RE4 :1;\r
- unsigned RE5 :1;\r
- unsigned :2;\r
- unsigned RE8 :1;\r
- unsigned :7;\r
-} PORTEBITS;\r
-extern volatile PORTEBITS PORTEbits __attribute__((__sfr__));\r
-\r
-/* LATE: Port E Latch Register */\r
-extern volatile unsigned int LATE __attribute__((__sfr__));\r
-typedef struct tagLATEBITS {\r
- unsigned LATE0 :1;\r
- unsigned LATE1 :1;\r
- unsigned LATE2 :1;\r
- unsigned LATE3 :1;\r
- unsigned LATE4 :1;\r
- unsigned LATE5 :1;\r
- unsigned :2;\r
- unsigned LATE8 :1;\r
- unsigned :7;\r
-} LATEBITS;\r
-extern volatile LATEBITS LATEbits __attribute__((__sfr__));\r
-\r
-/* TRISF: Port F Direction Control Register */\r
-extern volatile unsigned int TRISF __attribute__((__sfr__));\r
-typedef struct tagTRISFBITS {\r
- unsigned :2;\r
- unsigned TRISF2 :1;\r
- unsigned TRISF3 :1;\r
- unsigned :12;\r
-} TRISFBITS;\r
-extern volatile TRISFBITS TRISFbits __attribute__((__sfr__));\r
-\r
-/* PORTF: Port F Pin Register */\r
-extern volatile unsigned int PORTF __attribute__((__sfr__));\r
-typedef struct tagPORTFBITS {\r
- unsigned :2;\r
- unsigned RF2 :1;\r
- unsigned RF3 :1;\r
- unsigned :12;\r
-} PORTFBITS;\r
-extern volatile PORTFBITS PORTFbits __attribute__((__sfr__));\r
-\r
-/* LATF: Port F Latch Register */\r
-extern volatile unsigned int LATF __attribute__((__sfr__));\r
-typedef struct tagLATFBITS {\r
- unsigned :2;\r
- unsigned LATF2 :1;\r
- unsigned LATF3 :1;\r
- unsigned :12;\r
-} LATFBITS;\r
-extern volatile LATFBITS LATFbits __attribute__((__sfr__));\r
-\r
-\r
-/* ------------------------- */\r
-/* CAN1 register definitions */\r
-/* ------------------------- */\r
-\r
-/* Generic structure of entire SFR area for each CAN module */\r
-typedef struct tagCAN {\r
- unsigned int cxrxf0sid;\r
- unsigned int cxrxf0eidh;\r
- unsigned int cxrxf0eidl;\r
- unsigned int reserved0;\r
- unsigned int cxrxf1sid;\r
- unsigned int cxrxf1eidh;\r
- unsigned int cxrxf1eidl;\r
- unsigned int reserved1;\r
- unsigned int cxrxf2sid;\r
- unsigned int cxrxf2eidh;\r
- unsigned int cxrxf2eidl;\r
- unsigned int reserved2;\r
- unsigned int cxrxf3sid;\r
- unsigned int cxrxf3eidh;\r
- unsigned int cxrxf3eidl;\r
- unsigned int reserved3;\r
- unsigned int cxrxf4sid;\r
- unsigned int cxrxf4eidh;\r
- unsigned int cxrxf4eidl;\r
- unsigned int reserved4;\r
- unsigned int cxrxf5sid;\r
- unsigned int cxrxf5eidh;\r
- unsigned int cxrxf5eidl;\r
- unsigned int reserved5;\r
- unsigned int cxrxm0sid;\r
- unsigned int cxrxm0eidh;\r
- unsigned int cxrxm0eidl;\r
- unsigned int reserved6;\r
- unsigned int cxrxm1sid;\r
- unsigned int cxrxm1eidh;\r
- unsigned int cxrxm1eidl;\r
- unsigned int reserved7;\r
- unsigned int cxtx2sid;\r
- unsigned int cxtx2eid;\r
- unsigned int cxtx2dlc; \r
- unsigned int cxtx2b1;\r
- unsigned int cxtx2b2;\r
- unsigned int cxtx2b3;\r
- unsigned int cxtx2b4;\r
- unsigned int cxtx2con;\r
- unsigned int cxtx1sid;\r
- unsigned int cxtx1eid;\r
- unsigned int cxtx1dlc; \r
- unsigned int cxtx1b1;\r
- unsigned int cxtx1b2;\r
- unsigned int cxtx1b3;\r
- unsigned int cxtx1b4;\r
- unsigned int cxtx1con;\r
- unsigned int cxtx0sid;\r
- unsigned int cxtx0eid;\r
- unsigned int cxtx0dlc; \r
- unsigned int cxtx0b1;\r
- unsigned int cxtx0b2;\r
- unsigned int cxtx0b3;\r
- unsigned int cxtx0b4;\r
- unsigned int cxtx0con;\r
- unsigned int cxrx1sid;\r
- unsigned int cxrx1eid;\r
- unsigned int cxrx1dlc;\r
- unsigned int cxrx1b1;\r
- unsigned int cxrx1b2;\r
- unsigned int cxrx1b3;\r
- unsigned int cxrx1b4;\r
- unsigned int cxrx1con;\r
- unsigned int cxrx0sid;\r
- unsigned int cxrx0eid;\r
- unsigned int cxrx0dlc;\r
- unsigned int cxrx0b1;\r
- unsigned int cxrx0b2;\r
- unsigned int cxrx0b3;\r
- unsigned int cxrx0b4;\r
- unsigned int cxrx0con;\r
- unsigned int cxctrl;\r
- unsigned int cxcfg1;\r
- unsigned int cxcfg2;\r
- unsigned int cxintf;\r
- unsigned int cxinte;\r
- unsigned int cxec;\r
- unsigned int reserved8[50];\r
-} CAN, *PCAN;\r
-\r
-/* SFR blocks for each CAN module */\r
-extern volatile CAN CAN1 __attribute__((__sfr__));\r
-\r
-/* Generic structure for CAN Receive Filter Standard Identifier Register */\r
-typedef struct tagCxRXFxSIDBITS {\r
- unsigned EXIDE :1;\r
- unsigned :1; \r
- unsigned SID :11;\r
- unsigned :3;\r
-} CxRXFxSIDBITS;\r
-\r
-/* C1RXF0SID: CAN1 Receive Filter 0 SID Register */\r
-extern volatile unsigned int C1RXF0SID __attribute__((__sfr__));\r
-extern volatile CxRXFxSIDBITS C1RXF0SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RXF0EIDH: CAN1 Receive Filter 0 EIDH Register */\r
-extern volatile unsigned int C1RXF0EIDH __attribute__((__sfr__));\r
-\r
-/* C1RXF0EIDL: CAN1 Receive Filter 0 EIDL Register */\r
-extern volatile unsigned int C1RXF0EIDL __attribute__((__sfr__));\r
-\r
-/* C1RXF1SID: CAN1 Receive Filter 1 SID Register */\r
-extern volatile unsigned int C1RXF1SID __attribute__((__sfr__));\r
-extern volatile CxRXFxSIDBITS C1RXF1SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RXF1EIDH: CAN1 Receive Filter 1 EIDH Register */\r
-extern volatile unsigned int C1RXF1EIDH __attribute__((__sfr__));\r
-\r
-/* C1RXF1EIDL: CAN1 Receive Filter 1 EIDL Register */\r
-extern volatile unsigned int C1RXF1EIDL __attribute__((__sfr__));\r
-\r
-/* C1RXF2SID: CAN1 Receive Filter 2 SID Register */\r
-extern volatile unsigned int C1RXF2SID __attribute__((__sfr__));\r
-extern volatile CxRXFxSIDBITS C1RXF2SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RXF2EIDH: CAN1 Receive Filter 2 EIDH Register */\r
-extern volatile unsigned int C1RXF2EIDH __attribute__((__sfr__));\r
-\r
-/* C1RXF2EIDL: CAN1 Receive Filter 2 EIDL Register */\r
-extern volatile unsigned int C1RXF2EIDL __attribute__((__sfr__));\r
-\r
-/* C1RXF3SID: CAN1 Receive Filter 3 SID Register */\r
-extern volatile unsigned int C1RXF3SID __attribute__((__sfr__));\r
-extern volatile CxRXFxSIDBITS C1RXF3SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RXF3EIDH: CAN1 Receive Filter 3 EIDH Register */\r
-extern volatile unsigned int C1RXF3EIDH __attribute__((__sfr__));\r
-\r
-/* C1RXF3EIDL: CAN1 Receive Filter 3 EIDL Register */\r
-extern volatile unsigned int C1RXF3EIDL __attribute__((__sfr__));\r
-\r
-/* C1RXF4SID: CAN1 Receive Filter 4 SID Register */\r
-extern volatile unsigned int C1RXF4SID __attribute__((__sfr__));\r
-extern volatile CxRXFxSIDBITS C1RXF4SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RXF4EIDH: CAN1 Receive Filter 4 EIDH Register */\r
-extern volatile unsigned int C1RXF4EIDH __attribute__((__sfr__));\r
-\r
-/* C1RXF4EIDL: CAN1 Receive Filter 4 EIDL Register */\r
-extern volatile unsigned int C1RXF4EIDL __attribute__((__sfr__));\r
-\r
-/* C1RXF5SID: CAN1 Receive Filter 5 SID Register */\r
-extern volatile unsigned int C1RXF5SID __attribute__((__sfr__));\r
-extern volatile CxRXFxSIDBITS C1RXF5SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RXF5EIDH: CAN1 Receive Filter 5 EIDH Register */\r
-extern volatile unsigned int C1RXF5EIDH __attribute__((__sfr__)); \r
-\r
-/* C1RXF5EIDL: CAN1 Receive Filter 5 EIDL Register */\r
-extern volatile unsigned int C1RXF5EIDL __attribute__((__sfr__));\r
-\r
-/* Generic structure for CAN Receive Mask Standard Identifier Register */\r
-typedef struct tagCxRXMxSIDBITS {\r
- unsigned MIDE :1;\r
- unsigned :1; \r
- unsigned SID :11;\r
- unsigned :3;\r
-} CxRXMxSIDBITS;\r
-\r
-/* C1RXM0SID: CAN1 Receive Mask 0 SID Register */\r
-extern volatile unsigned int C1RXM0SID __attribute__((__sfr__));\r
-extern volatile CxRXMxSIDBITS C1RXM0SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RXM0EIDH: CAN1 Receive Mask 0 EIDH Register */\r
-extern volatile unsigned int C1RXM0EIDH __attribute__((__sfr__));\r
-\r
-/* C1RXM0EIDL: CAN1 Receive Mask 0 EIDL Register */\r
-extern volatile unsigned int C1RXM0EIDL __attribute__((__sfr__));\r
-\r
-/* C1RXM1SID: CAN1 Receive Mask 1 SID Register */\r
-extern volatile unsigned int C1RXM1SID __attribute__((__sfr__));\r
-extern volatile CxRXMxSIDBITS C1RXM1SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RXM1EIDH: CAN1 Receive Mask 1 EIDH Register */\r
-extern volatile unsigned int C1RXM1EIDH __attribute__((__sfr__));\r
-\r
-/* C1RXM1EIDL: CAN1 Receive Mask 1 EIDL Register */\r
-extern volatile unsigned int C1RXM1EIDL __attribute__((__sfr__));\r
-\r
-/* Generic structure for CAN Transmit Standard Identifier Register */\r
-typedef struct tagCxTXxSIDBITS {\r
- unsigned TXIDE :1;\r
- unsigned SRR :1;\r
- unsigned SID5_0 :6;\r
- unsigned :3;\r
- unsigned SID10_6:5;\r
-} CxTXxSIDBITS;\r
-\r
-/* Generic structure for CAN Transmit Extended Identifier Register */\r
-typedef struct tagCxTXxEIDBITS {\r
- unsigned EID13_6:8;\r
- unsigned :4;\r
- unsigned EID17_14:4;\r
-} CxTXxEIDBITS;\r
-\r
-/* Generic structure for CAN Transmit Data Length Code Register */\r
-typedef struct tagCxTXxDLCBITS {\r
- unsigned :3;\r
- unsigned DLC :4;\r
- unsigned TXRB0 :1;\r
- unsigned TXRB1 :1;\r
- unsigned TXRTR :1;\r
- unsigned EID5_0 :6;\r
-} CxTXxDLCBITS;\r
-\r
-/* Generic structure for CAN Transmit Control Register */\r
-typedef struct tagCxTXxCONBITS {\r
- unsigned TXPRI :2;\r
- unsigned :1;\r
- unsigned TXREQ :1;\r
- unsigned TXERR :1;\r
- unsigned TXLARB :1;\r
- unsigned TXABT :1;\r
- unsigned :9;\r
-} CxTXxCONBITS;\r
-\r
-/* C1TX2SID: CAN1 Transmit 2 SID Register */\r
-extern volatile unsigned int C1TX2SID __attribute__((__sfr__));\r
-extern volatile CxTXxSIDBITS C1TX2SIDbits __attribute__((__sfr__));\r
-\r
-/* C1TX2EID: CAN1 Transmit 2 EID Register */\r
-extern volatile unsigned int C1TX2EID __attribute__((__sfr__));\r
-extern volatile CxTXxEIDBITS C1TX2EIDbits __attribute__((__sfr__));\r
-\r
-/* C1TX2DLC: CAN1 Transmit 2 DLC Register */\r
-extern volatile unsigned int C1TX2DLC __attribute__((__sfr__));\r
-extern volatile CxTXxDLCBITS C1TX2DLCbits __attribute__((__sfr__));\r
-\r
-/* C1TX2B1: CAN1 Transmit 2 Buffer Word 1 */\r
-extern volatile unsigned int C1TX2B1 __attribute__((__sfr__));\r
-\r
-/* C1TX2B2: CAN1 Transmit 2 Buffer Word 2 */\r
-extern volatile unsigned int C1TX2B2 __attribute__((__sfr__));\r
-\r
-/* C1TX2B3: CAN1 Transmit 2 Buffer Word 3 */\r
-extern volatile unsigned int C1TX2B3 __attribute__((__sfr__));\r
-\r
-/* C1TX2B4: CAN1 Transmit 2 Buffer Word 4 */\r
-extern volatile unsigned int C1TX2B4 __attribute__((__sfr__));\r
-\r
-/* C1TX2CON: CAN1 Transmit 2 Control Register */\r
-extern volatile unsigned int C1TX2CON __attribute__((__sfr__));\r
-extern volatile CxTXxCONBITS C1TX2CONbits __attribute__((__sfr__));\r
-\r
-/* C1TX1SID: CAN1 Transmit 1 SID Register */\r
-extern volatile unsigned int C1TX1SID __attribute__((__sfr__));\r
-extern volatile CxTXxSIDBITS C1TX1SIDbits __attribute__((__sfr__));\r
-\r
-/* C1TX1EID: CAN1 Transmit 1 EID Register */\r
-extern volatile unsigned int C1TX1EID __attribute__((__sfr__));\r
-extern volatile CxTXxEIDBITS C1TX1EIDbits __attribute__((__sfr__));\r
-\r
-/* C1TX1DLC: CAN1 Transmit 1 DLC Register */\r
-extern volatile unsigned int C1TX1DLC __attribute__((__sfr__));\r
-extern volatile CxTXxDLCBITS C1TX1DLCbits __attribute__((__sfr__));\r
-\r
-/* C1TX1B1: CAN1 Transmit 1 Buffer Word 1 */\r
-extern volatile unsigned int C1TX1B1 __attribute__((__sfr__));\r
-\r
-/* C1TX1B2: CAN1 Transmit 1 Buffer Word 2 */\r
-extern volatile unsigned int C1TX1B2 __attribute__((__sfr__));\r
-\r
-/* C1TX1B3: CAN1 Transmit 1 Buffer Word 3 */\r
-extern volatile unsigned int C1TX1B3 __attribute__((__sfr__));\r
-\r
-/* C1TX1B4: CAN1 Transmit 1 Buffer Word 4 */\r
-extern volatile unsigned int C1TX1B4 __attribute__((__sfr__));\r
-\r
-/* C1TX1CON: CAN1 Transmit 1 Control Register */\r
-extern volatile unsigned int C1TX1CON __attribute__((__sfr__));\r
-extern volatile CxTXxCONBITS C1TX1CONbits __attribute__((__sfr__));\r
-\r
-/* C1TX0SID: CAN1 Transmit 0 SID Register */\r
-extern volatile unsigned int C1TX0SID __attribute__((__sfr__));\r
-extern volatile CxTXxSIDBITS C1TX0SIDbits __attribute__((__sfr__));\r
-\r
-/* C1TX0EID: CAN1 Transmit 0 EID Register */\r
-extern volatile unsigned int C1TX0EID __attribute__((__sfr__));\r
-extern volatile CxTXxEIDBITS C1TX0EIDbits __attribute__((__sfr__));\r
-\r
-/* C1TX0DLC: CAN1 Transmit 0 DLC Register */\r
-extern volatile unsigned int C1TX0DLC __attribute__((__sfr__));\r
-extern volatile CxTXxDLCBITS C1TX0DLCbits __attribute__((__sfr__));\r
-\r
-/* C1TX0B1: CAN1 Transmit 0 Buffer Word 1 */\r
-extern volatile unsigned int C1TX0B1 __attribute__((__sfr__));\r
-\r
-/* C1TX0B2: CAN1 Transmit 0 Buffer Word 2 */\r
-extern volatile unsigned int C1TX0B2 __attribute__((__sfr__));\r
-\r
-/* C1TX0B3: CAN1 Transmit 0 Buffer Word 3 */\r
-extern volatile unsigned int C1TX0B3 __attribute__((__sfr__));\r
-\r
-/* C1TX0B4: CAN1 Transmit 0 Buffer Word 4 */\r
-extern volatile unsigned int C1TX0B4 __attribute__((__sfr__));\r
-\r
-/* C1TX0CON: CAN1 Transmit 0 Control Register */\r
-extern volatile unsigned int C1TX0CON __attribute__((__sfr__));\r
-extern volatile CxTXxCONBITS C1TX0CONbits __attribute__((__sfr__));\r
-\r
-/* Generic structure for CAN Receive Standard Identifier Register */\r
-typedef struct tagCxRXxSIDBITS {\r
- unsigned RXIDE :1;\r
- unsigned SRR :1;\r
- unsigned SID :11;\r
- unsigned :3;\r
-} CxRXxSIDBITS;\r
-\r
-/* Generic structure for CAN Receive Data Length Code Register */\r
-typedef struct tagCxRXxDLCBITS {\r
- unsigned DLC :4;\r
- unsigned RXRB0 :1;\r
- unsigned :3;\r
- unsigned RXRB1 :1;\r
- unsigned RXRTR :1;\r
- unsigned EID5_0 :6;\r
-} CxRXxDLCBITS;\r
-\r
-/* Generic structure for CAN Receive 1 Control Register */\r
-typedef struct tagCxRX1CONBITS {\r
- unsigned FILHIT :3;\r
- unsigned RXRTRRO:1;\r
- unsigned :3;\r
- unsigned RXFUL :1;\r
- unsigned :8;\r
-} CxRX1CONBITS;\r
-\r
-/* C1RX1SID: CAN1 Receive 1 SID Register */\r
-extern volatile unsigned int C1RX1SID __attribute__((__sfr__));\r
-extern volatile CxRXxSIDBITS C1RX1SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RX1EID: CAN1 Receive 1 EID Register */\r
-extern volatile unsigned int C1RX1EID __attribute__((__sfr__));\r
-\r
-/* C1RX1DLC: CAN1 Receive 1 DLC Register */\r
-extern volatile unsigned int C1RX1DLC __attribute__((__sfr__));\r
-extern volatile CxRXxDLCBITS C1RX1DLCbits __attribute__((__sfr__));\r
-\r
-/* C1RX1B1: CAN1 Receive 1 Buffer Word 1 */\r
-extern volatile unsigned int C1RX1B1 __attribute__((__sfr__));\r
-\r
-/* C1RX1B2: CAN1 Receive 1 Buffer Word 2 */\r
-extern volatile unsigned int C1RX1B2 __attribute__((__sfr__));\r
-\r
-/* C1RX1B3: CAN1 Receive 1 Buffer Word 3 */\r
-extern volatile unsigned int C1RX1B3 __attribute__((__sfr__));\r
-\r
-/* C1RX1B4: CAN1 Receive 1 Buffer Word 4 */\r
-extern volatile unsigned int C1RX1B4 __attribute__((__sfr__));\r
-\r
-/* C1RX1CON: CAN1 Receive 1 Control Register */\r
-extern volatile unsigned int C1RX1CON __attribute__((__sfr__));\r
-extern volatile CxRX1CONBITS C1RX1CONbits __attribute__((__sfr__));\r
-\r
-/* Generic structure for CAN Receive 0 Control Register */\r
-typedef struct tagCxRX0CONBITS {\r
- unsigned FILHIT0:1;\r
- unsigned JTOFF :1;\r
- unsigned DBEN :1;\r
- unsigned RXRTRRO:1;\r
- unsigned :3;\r
- unsigned RXFUL :1;\r
- unsigned :8;\r
-} CxRX0CONBITS;\r
-\r
-/* C1RX0SID: CAN1 Receive 0 SID Register */\r
-extern volatile unsigned int C1RX0SID __attribute__((__sfr__));\r
-extern volatile CxRXxSIDBITS C1RX0SIDbits __attribute__((__sfr__));\r
-\r
-/* C1RX0EID: CAN1 Receive 0 EID Register */\r
-extern volatile unsigned int C1RX0EID __attribute__((__sfr__));\r
-\r
-/* C1RX0DLC: CAN1 Receive 0 DLC Register */\r
-extern volatile unsigned int C1RX0DLC __attribute__((__sfr__));\r
-extern volatile CxRXxDLCBITS C1RX0DLCbits __attribute__((__sfr__));\r
-\r
-/* C1RX0B1: CAN1 Receive 0 Buffer Word 1 */\r
-extern volatile unsigned int C1RX0B1 __attribute__((__sfr__));\r
-\r
-/* C1RX0B2: CAN1 Receive 0 Buffer Word 2 */\r
-extern volatile unsigned int C1RX0B2 __attribute__((__sfr__));\r
-\r
-/* C1RX0B3: CAN1 Receive 0 Buffer Word 3 */\r
-extern volatile unsigned int C1RX0B3 __attribute__((__sfr__));\r
-\r
-/* C1RX0B4: CAN1 Receive 0 Buffer Word 4 */\r
-extern volatile unsigned int C1RX0B4 __attribute__((__sfr__));\r
-\r
-/* C1RX0CON: CAN1 Receive 0 Control Register */\r
-extern volatile unsigned int C1RX0CON __attribute__((__sfr__));\r
-extern volatile CxRX0CONBITS C1RX0CONbits __attribute__((__sfr__));\r
-\r
-/* C1CTRL: CAN1 Control Register */\r
-extern volatile unsigned int C1CTRL __attribute__((__sfr__));\r
-typedef struct tagCxCTRLBITS {\r
- unsigned :1;\r
- unsigned ICODE :3;\r
- unsigned :1;\r
- unsigned OPMODE :3;\r
- unsigned REQOP :3;\r
- unsigned CANCKS :1;\r
- unsigned ABAT :1;\r
- unsigned CSIDL :1;\r
- unsigned :1;\r
- unsigned CANCAP :1;\r
-} CxCTRLBITS;\r
-extern volatile CxCTRLBITS C1CTRLbits __attribute__((__sfr__));\r
-\r
-/* C1CFG1: CAN1 Baud Rate Control Register 1 */\r
-extern volatile unsigned int C1CFG1 __attribute__((__sfr__));\r
-typedef struct tagCxCFG1BITS {\r
- unsigned BRP :6;\r
- unsigned SJW :2;\r
- unsigned :8;\r
-} CxCFG1BITS;\r
-extern volatile CxCFG1BITS C1CFG1bits __attribute__((__sfr__));\r
-\r
-/* C1CFG2: CAN1 Baud Rate Control Register 2 */\r
-extern volatile unsigned int C1CFG2 __attribute__((__sfr__));\r
-typedef struct tagCxCFG2BITS {\r
- unsigned PRSEG :3;\r
- unsigned SEG1PH :3;\r
- unsigned SAM :1;\r
- unsigned SEG2PHTS:1;\r
- unsigned SEG2PH :3;\r
- unsigned :3;\r
- unsigned WAKFIL :1;\r
- unsigned :1;\r
-} CxCFG2BITS;\r
-extern volatile CxCFG2BITS C1CFG2bits __attribute__((__sfr__));\r
-\r
-/* C1INTF: CAN1 Interrupt Flag Status Register */\r
-extern volatile unsigned int C1INTF __attribute__((__sfr__));\r
-typedef struct tagCxINTFBITS {\r
- unsigned RX0IF :1;\r
- unsigned RX1IF :1;\r
- unsigned TX0IF :1;\r
- unsigned TX1IF :1;\r
- unsigned TX2IF :1;\r
- unsigned ERRIF :1;\r
- unsigned WAKIF :1;\r
- unsigned IVRIF :1;\r
- unsigned EWARN :1;\r
- unsigned RXWAR :1;\r
- unsigned TXWAR :1;\r
- unsigned RXEP :1;\r
- unsigned TXEP :1;\r
- unsigned TXBO :1;\r
- unsigned RX1OVR :1;\r
- unsigned RX0OVR :1;\r
-} CxINTFBITS;\r
-extern volatile CxINTFBITS C1INTFbits __attribute__((__sfr__));\r
-\r
-/* C1INTE: CAN1 Interrupt Enable Control Register */\r
-extern volatile unsigned int C1INTE __attribute__((__sfr__));\r
-typedef struct tagCxINTEBITS {\r
- unsigned RX0IE :1;\r
- unsigned RX1IE :1;\r
- unsigned TX0IE :1;\r
- unsigned TX1IE :1;\r
- unsigned TX2IE :1;\r
- unsigned ERRIE :1;\r
- unsigned WAKIE :1;\r
- unsigned IVRIE :1;\r
- unsigned :8;\r
-} CxINTEBITS;\r
-extern volatile CxINTEBITS C1INTEbits __attribute__((__sfr__));\r
-\r
-/* C1EC: CAN1 Error Count Register */\r
-extern volatile unsigned int C1EC __attribute__((__sfr__));\r
-\r
-/* C1RERRCNT: CAN1 Receive Error Count (C1EC low byte) */\r
-extern volatile unsigned char C1RERRCNT __attribute__((__sfr__));\r
-\r
-/* C1TERRCNT: CAN1 Transmit Error Count (C1EC high byte) */\r
-extern volatile unsigned char C1TERRCNT __attribute__((__sfr__));\r
-\r
-\r
-/* --------------------------------------- */\r
-/* System Integration register definitions */\r
-/* --------------------------------------- */\r
-\r
-/* RCON: Reset Control Register */\r
-extern volatile unsigned int RCON __attribute__((__sfr__));\r
-typedef struct tagRCONBITS {\r
- unsigned POR :1;\r
- unsigned BOR :1;\r
- unsigned IDLE :1;\r
- unsigned SLEEP :1;\r
- unsigned WDTO :1;\r
- unsigned SWDTEN :1;\r
- unsigned SWR :1;\r
- unsigned EXTR :1;\r
- unsigned :5;\r
- unsigned BGST :1;\r
- unsigned IOPUWR :1;\r
- unsigned TRAPR :1;\r
-} RCONBITS;\r
-extern volatile RCONBITS RCONbits __attribute__((__sfr__));\r
-\r
-/* OSCCON: Oscillator Control Register */\r
-extern volatile unsigned int OSCCON __attribute__((__sfr__));\r
-typedef struct tagOSCCONBITS {\r
- unsigned OSWEN :1;\r
- unsigned LPOSCEN:1;\r
- unsigned :1;\r
- unsigned CF :1;\r
- unsigned :1;\r
- unsigned LOCK :1;\r
- unsigned POST :2;\r
- unsigned NOSC :2;\r
- unsigned TUN0 :1;\r
- unsigned TUN1 :1;\r
- unsigned COSC :2;\r
- unsigned TUN2 :1;\r
- unsigned TUN3 :1;\r
-} OSCCONBITS;\r
-extern volatile OSCCONBITS OSCCONbits __attribute__((__sfr__));\r
-\r
-\r
-/* ---------------------------------------- */\r
-/* Non-Volatile Memory register definitions */\r
-/* ---------------------------------------- */\r
-\r
-/* NVMCON: Non-Volatile Memory Control Register */\r
-extern volatile unsigned int NVMCON __attribute__((__sfr__));\r
-typedef struct tagNVMCONBITS {\r
- unsigned PROGOP :7;\r
- unsigned :1;\r
- unsigned TWRI :1;\r
- unsigned :4;\r
- unsigned WRERR :1;\r
- unsigned WREN :1;\r
- unsigned WR :1;\r
-} NVMCONBITS;\r
-extern volatile NVMCONBITS NVMCONbits __attribute__((__sfr__));\r
-\r
-/* NVM Address bits <15:0> */\r
-extern volatile unsigned int NVMADR __attribute__((__sfr__));\r
-\r
-/* NVM Address bits <23:16> */\r
-extern volatile unsigned char NVMADRU __attribute__((__sfr__));\r
-\r
-/* NVM Key */\r
-extern volatile unsigned char NVMKEY __attribute__((__sfr__));\r
-\r
-\r
-/* ---------------------------------------------- */\r
-/* Peripheral Module Disable register definitions */\r
-/* ---------------------------------------------- */\r
-\r
-/* PMD1: Peripheral Module Disable Register 1 */\r
-extern volatile unsigned int PMD1 __attribute__((__sfr__));\r
-typedef struct tagPMD1BITS {\r
- unsigned ADCMD :1;\r
- unsigned C1MD :1;\r
- unsigned :1;\r
- unsigned SPI1MD :1;\r
- unsigned :1;\r
- unsigned U1MD :1;\r
- unsigned :1;\r
- unsigned I2CMD :1;\r
- unsigned :1;\r
- unsigned PWMMD :1;\r
- unsigned QEIMD :1;\r
- unsigned T1MD :1;\r
- unsigned T2MD :1;\r
- unsigned T3MD :1;\r
- unsigned T4MD :1;\r
- unsigned T5MD :1;\r
-} PMD1BITS;\r
-extern volatile PMD1BITS PMD1bits __attribute__((__sfr__));\r
-\r
-/* PMD2: Peripheral Module Disable Register 3 */\r
-extern volatile unsigned int PMD2 __attribute__((__sfr__));\r
-typedef struct tagPMD2BITS {\r
- unsigned OC1MD :1;\r
- unsigned OC2MD :1;\r
- unsigned :6;\r
- unsigned IC1MD :1;\r
- unsigned IC2MD :1;\r
- unsigned :4;\r
- unsigned IC7MD :1;\r
- unsigned IC8MD :1;\r
-} PMD2BITS;\r
-extern volatile PMD2BITS PMD2bits __attribute__((__sfr__));\r
-\r
-\r
-/* -------------------------------------------- */ \r
-/* Defines for unique SFR bit names */\r
-/* -------------------------------------------- */\r
-\r
-/* SR */\r
-#define _C SRbits.C\r
-#define _Z SRbits.Z\r
-#define _OV SRbits.OV\r
-#define _N SRbits.N\r
-#define _RA SRbits.RA\r
-#define _IPL SRbits.IPL\r
-#define _DC SRbits.DC\r
-#define _DA SRbits.DA\r
-#define _SAB SRbits.SAB\r
-#define _OAB SRbits.OAB\r
-#define _SB SRbits.SB\r
-#define _SA SRbits.SA\r
-#define _OB SRbits.OB\r
-#define _OA SRbits.OA\r
-\r
-/* CORCON */\r
-#define _IF CORCONbits.IF\r
-#define _RND CORCONbits.RND\r
-#define _PSV CORCONbits.PSV\r
-#define _IPL3 CORCONbits.IPL3\r
-#define _ACCSAT CORCONbits.ACCSAT\r
-#define _SATDW CORCONbits.SATDW\r
-#define _SATB CORCONbits.SATB\r
-#define _SATA CORCONbits.SATA\r
-#define _DL CORCONbits.DL\r
-#define _EDT CORCONbits.EDT\r
-#define _US CORCONbits.US\r
-\r
-/* MODCON */\r
-#define _XWM MODCONbits.XWM\r
-#define _YWM MODCONbits.YWM\r
-#define _BWM MODCONbits.BWM\r
-#define _YMODEN MODCONbits.YMODEN\r
-#define _XMODEN MODCONbits.XMODEN\r
-\r
-/* XBREV */\r
-#define _XB XBREVbits.XB\r
-#define _BREN XBREVbits.BREN\r
-\r
-/* INTCON1 */\r
-#define _OSCFAIL INTCON1bits.OSCFAIL\r
-#define _STKERR INTCON1bits.STKERR\r
-#define _ADDRERR INTCON1bits.ADDRERR\r
-#define _MATHERR INTCON1bits.MATHERR\r
-#define _COVTE INTCON1bits.COVTE\r
-#define _OVBTE INTCON1bits.OVBTE\r
-#define _OVATE INTCON1bits.OVATE\r
-#define _NSTDIS INTCON1bits.NSTDIS\r
-\r
-/* INTCON2 */\r
-#define _INT0EP INTCON2bits.INT0EP\r
-#define _INT1EP INTCON2bits.INT1EP\r
-#define _INT2EP INTCON2bits.INT2EP\r
-#define _DISI INTCON2bits.DISI\r
-#define _ALTIVT INTCON2bits.ALTIVT\r
-\r
-/* IFS0 */\r
-#define _INT0IF IFS0bits.INT0IF \r
-#define _IC1IF IFS0bits.IC1IF\r
-#define _OC1IF IFS0bits.OC1IF\r
-#define _T1IF IFS0bits.T1IF\r
-#define _IC2IF IFS0bits.IC2IF\r
-#define _OC2IF IFS0bits.OC2IF\r
-#define _T2IF IFS0bits.T2IF\r
-#define _T3IF IFS0bits.T3IF\r
-#define _SPI1IF IFS0bits.SPI1IF \r
-#define _U1RXIF IFS0bits.U1RXIF\r
-#define _U1TXIF IFS0bits.U1TXIF\r
-#define _ADIF IFS0bits.ADIF\r
-#define _NVMIF IFS0bits.NVMIF\r
-#define _SI2CIF IFS0bits.SI2CIF\r
-#define _MI2CIF IFS0bits.MI2CIF\r
-#define _CNIF IFS0bits.CNIF\r
-\r
-/* IFS1 */\r
-#define _INT1IF IFS1bits.INT1IF \r
-#define _IC7IF IFS1bits.IC7IF\r
-#define _IC8IF IFS1bits.IC8IF\r
-#define _T4IF IFS1bits.T4IF\r
-#define _T5IF IFS1bits.T5IF\r
-#define _INT2IF IFS1bits.INT2IF\r
-#define _C1IF IFS1bits.C1IF\r
-\r
-/* IFS2 */\r
-#define _PWMIF IFS2bits.PWMIF\r
-#define _QEIIF IFS2bits.QEIIF\r
-#define _FLTAIF IFS2bits.FLTAIF \r
-\r
-/* IEC0 */\r
-#define _INT0IE IEC0bits.INT0IE \r
-#define _IC1IE IEC0bits.IC1IE\r
-#define _OC1IE IEC0bits.OC1IE\r
-#define _T1IE IEC0bits.T1IE\r
-#define _IC2IE IEC0bits.IC2IE\r
-#define _OC2IE IEC0bits.OC2IE\r
-#define _T2IE IEC0bits.T2IE\r
-#define _T3IE IEC0bits.T3IE\r
-#define _SPI1IE IEC0bits.SPI1IE \r
-#define _U1RXIE IEC0bits.U1RXIE\r
-#define _U1TXIE IEC0bits.U1TXIE\r
-#define _ADIE IEC0bits.ADIE\r
-#define _NVMIE IEC0bits.NVMIE\r
-#define _SI2CIE IEC0bits.SI2CIE\r
-#define _MI2CIE IEC0bits.MI2CIE\r
-#define _CNIE IEC0bits.CNIE\r
-\r
-/* IEC1 */\r
-#define _INT1IE IEC1bits.INT1IE \r
-#define _IC7IE IEC1bits.IC7IE\r
-#define _IC8IE IEC1bits.IC8IE\r
-#define _T4IE IEC1bits.T4IE\r
-#define _T5IE IEC1bits.T5IE\r
-#define _INT2IE IEC1bits.INT2IE\r
-#define _C1IE IEC1bits.C1IE\r
-\r
-/* IEC2 */\r
-#define _PWMIE IEC2bits.PWMIE\r
-#define _QEIIE IEC2bits.QEIIE\r
-#define _FLTAIE IEC2bits.FLTAIE \r
-\r
-/* IPC0 */\r
-#define _INT0IP IPC0bits.INT0IP \r
-#define _IC1IP IPC0bits.IC1IP\r
-#define _OC1IP IPC0bits.OC1IP\r
-#define _T1IP IPC0bits.T1IP\r
-\r
-/* IPC1 */\r
-#define _IC2IP IPC1bits.IC2IP \r
-#define _OC2IP IPC1bits.OC2IP\r
-#define _T2IP IPC1bits.T2IP\r
-#define _T3IP IPC1bits.T3IP\r
-\r
-/* IPC2 */\r
-#define _SPI1IP IPC2bits.SPI1IP \r
-#define _U1RXIP IPC2bits.U1RXIP\r
-#define _U1TXIP IPC2bits.U1TXIP\r
-#define _ADIP IPC2bits.ADIP\r
-\r
-/* IPC3 */\r
-#define _NVMIP IPC3bits.NVMIP \r
-#define _SI2CIP IPC3bits.SI2CIP\r
-#define _MI2CIP IPC3bits.MI2CIP\r
-#define _CNIP IPC3bits.CNIP\r
-\r
-/* IPC4 */\r
-#define _INT1IP IPC4bits.INT1IP \r
-#define _IC7IP IPC4bits.IC7IP\r
-#define _IC8IP IPC4bits.IC8IP\r
-\r
-/* IPC5 */\r
-#define _T4IP IPC5bits.T4IP\r
-#define _T5IP IPC5bits.T5IP\r
-#define _INT2IP IPC5bits.INT2IP\r
-\r
-/* IPC6 */\r
-#define _C1IP IPC6bits.C1IP\r
-\r
-/* IPC9 */\r
-#define _PWMIP IPC9bits.PWMIP\r
-\r
-/* IPC10 */\r
-#define _QEIIP IPC10bits.QEIIP\r
-#define _FLTAIP IPC10bits.FLTAIP\r
-\r
-/* CNEN1 */\r
-#define _CN0IE CNEN1bits.CN0IE \r
-#define _CN1IE CNEN1bits.CN1IE\r
-#define _CN2IE CNEN1bits.CN2IE\r
-#define _CN3IE CNEN1bits.CN3IE\r
-#define _CN4IE CNEN1bits.CN4IE\r
-#define _CN5IE CNEN1bits.CN5IE\r
-#define _CN6IE CNEN1bits.CN6IE\r
-#define _CN7IE CNEN1bits.CN7IE\r
-\r
-/* CNPU1 */\r
-#define _CN0PUE CNPU1bits.CN0PUE \r
-#define _CN1PUE CNPU1bits.CN1PUE\r
-#define _CN2PUE CNPU1bits.CN2PUE\r
-#define _CN3PUE CNPU1bits.CN3PUE\r
-#define _CN4PUE CNPU1bits.CN4PUE\r
-#define _CN5PUE CNPU1bits.CN5PUE\r
-#define _CN6PUE CNPU1bits.CN6PUE\r
-#define _CN7PUE CNPU1bits.CN7PUE\r
-\r
-/* QEICON */\r
-#define _UPDN_SRC QEICONbits.UPDN_SRC\r
-#define _TQCS QEICONbits.TQCS\r
-#define _POSRES QEICONbits.POSRES\r
-#define _TQCKPS QEICONbits.TQCKPS\r
-#define _TQGATE QEICONbits.TQGATE\r
-#define _PCDOUT QEICONbits.PCDOUT\r
-#define _SWPAB QEICONbits.SWPAB\r
-#define _QEIM QEICONbits.QEIM\r
-#define _UPDN QEICONbits.UPDN\r
-#define _INDX QEICONbits.INDX\r
-#define _QEISIDL QEICONbits.QEISIDL\r
-#define _CNTERR QEICONbits.CNTERR\r
-\r
-/* DFLTCON */\r
-#define _QECK DFLTCONbits.QECK\r
-#define _QEOUT DFLTCONbits.QEOUT\r
-#define _CEID DFLTCONbits.CEID\r
-#define _IMV DFLTCONbits.IMV\r
-\r
-/* PTCON */\r
-#define _PTMOD PTCONbits.PTMOD\r
-#define _PTCKPS PTCONbits.PTCKPS\r
-#define _PTOPS PTCONbits.PTOPS\r
-#define _PTSIDL PTCONbits.PTSIDL\r
-#define _PTEN PTCONbits.PTEN\r
-\r
-/* PTMR */\r
-#define _PTDIR PTMRbits.PTDIR\r
-\r
-/* SEVTCMP */\r
-#define _SEVTDIR SEVTCMPbits.SEVTDIR\r
-\r
-/* PWMCON1 */\r
-#define _PEN1L PWMCON1bits.PEN1L\r
-#define _PEN2L PWMCON1bits.PEN2L\r
-#define _PEN3L PWMCON1bits.PEN3L\r
-#define _PEN1H PWMCON1bits.PEN1H\r
-#define _PEN2H PWMCON1bits.PEN2H\r
-#define _PEN3H PWMCON1bits.PEN3H\r
-#define _PMOD1 PWMCON1bits.PMOD1\r
-#define _PMOD2 PWMCON1bits.PMOD2\r
-#define _PMOD3 PWMCON1bits.PMOD3\r
-\r
-/* PWMCON2 */\r
-#define _UDIS PWMCON2bits.UDIS\r
-#define _OSYNC PWMCON2bits.OSYNC\r
-#define _SEVOPS PWMCON2bits.SEVOPS\r
-\r
-/* DTCON1 */\r
-#define _DTA DTCON1bits.DTA\r
-#define _DTAPS DTCON1bits.DTAPS\r
-\r
-/* FLTACON */\r
-#define _FAEN1 FLTACONbits.FAEN1\r
-#define _FAEN2 FLTACONbits.FAEN2\r
-#define _FAEN3 FLTACONbits.FAEN3\r
-#define _FLTAM FLTACONbits.FLTAM\r
-#define _FAOV1L FLTACONbits.FAOV1L\r
-#define _FAOV1H FLTACONbits.FAOV1H\r
-#define _FAOV2L FLTACONbits.FAOV2L\r
-#define _FAOV2H FLTACONbits.FAOV2H\r
-#define _FAOV3L FLTACONbits.FAOV3L\r
-#define _FAOV3H FLTACONbits.FAOV3H\r
-\r
-/* FLTBCON */\r
-#define _FBEN1 FLTBCONbits.FBEN1\r
-#define _FBEN2 FLTBCONbits.FBEN2\r
-#define _FBEN3 FLTBCONbits.FBEN3\r
-#define _FLTBM FLTBCONbits.FLTBM\r
-#define _FBOV1L FLTBCONbits.FBOV1L\r
-#define _FBOV1H FLTBCONbits.FBOV1H\r
-#define _FBOV2L FLTBCONbits.FBOV2L\r
-#define _FBOV2H FLTBCONbits.FBOV2H\r
-#define _FBOV3L FLTBCONbits.FBOV3L\r
-#define _FBOV3H FLTBCONbits.FBOV3H\r
-\r
-/* OVDCON */\r
-#define _POUT1L OVDCONbits.POUT1L\r
-#define _POUT1H OVDCONbits.POUT1H\r
-#define _POUT2L OVDCONbits.POUT2L\r
-#define _POUT2H OVDCONbits.POUT2H\r
-#define _POUT3L OVDCONbits.POUT3L\r
-#define _POUT3H OVDCONbits.POUT3H\r
-#define _POVD1L OVDCONbits.POVD1L\r
-#define _POVD1H OVDCONbits.POVD1H\r
-#define _POVD2L OVDCONbits.POVD2L\r
-#define _POVD2H OVDCONbits.POVD2H\r
-#define _POVD3L OVDCONbits.POVD3L\r
-#define _POVD3H OVDCONbits.POVD3H\r
-\r
-/* I2CCON */\r
-#define _SEN I2CCONbits.SEN\r
-#define _RSEN I2CCONbits.RSEN\r
-#define _PEN I2CCONbits.PEN\r
-#define _RCEN I2CCONbits.RCEN\r
-#define _ACKEN I2CCONbits.ACKEN\r
-#define _ACKDT I2CCONbits.ACKDT\r
-#define _STREN I2CCONbits.STREN\r
-#define _GCEN I2CCONbits.GCEN\r
-#define _SMEN I2CCONbits.SMEN\r
-#define _DISSLW I2CCONbits.DISSLW\r
-#define _A10M I2CCONbits.A10M\r
-#define _IPMIEN I2CCONbits.IPMIEN\r
-#define _SCLREL I2CCONbits.SCLREL\r
-#define _I2CSIDL I2CCONbits.I2CSIDL\r
-#define _I2CEN I2CCONbits.I2CEN\r
-\r
-/* I2CSTAT */\r
-#define _TBF I2CSTATbits.TBF\r
-#define _RBF I2CSTATbits.RBF\r
-#define _R_W I2CSTATbits.R_W\r
-#define _S I2CSTATbits.S\r
-#define _P I2CSTATbits.P\r
-#define _D_A I2CSTATbits.D_A\r
-#define _I2COV I2CSTATbits.I2COV\r
-#define _IWCOL I2CSTATbits.IWCOL\r
-#define _ADD10 I2CSTATbits.ADD10\r
-#define _GCSTAT I2CSTATbits.GCSTAT\r
-#define _BCL I2CSTATbits.BCL\r
-#define _TRSTAT I2CSTATbits.TRSTAT\r
-#define _ACKSTAT I2CSTATbits.ACKSTAT\r
-\r
-/* ADCON1 */\r
-#define _DONE ADCON1bits.DONE\r
-#define _SAMP ADCON1bits.SAMP\r
-#define _ASAM ADCON1bits.ASAM\r
-#define _SIMSAM ADCON1bits.SIMSAM\r
-#define _SSRC ADCON1bits.SSRC\r
-#define _FORM ADCON1bits.FORM\r
-#define _ADSIDL ADCON1bits.ADSIDL\r
-#define _ADON ADCON1bits.ADON\r
-\r
-/* ADCON2 */\r
-#define _ALTS ADCON2bits.ALTS\r
-#define _BUFM ADCON2bits.BUFM\r
-#define _SMPI ADCON2bits.SMPI\r
-#define _BUFS ADCON2bits.BUFS\r
-#define _CSCNA ADCON2bits.CSCNA\r
-#define _VCFG ADCON2bits.VCFG\r
-\r
-/* ADCON3 */\r
-#define _ADCS ADCON3bits.ADCS\r
-#define _ADRC ADCON3bits.ADRC\r
-#define _SAMC ADCON3bits.SAMC\r
-\r
-/* ADCHS */\r
-#define _CH0SA ADCHSbits.CH0SA\r
-#define _CH0NA ADCHSbits.CH0NA\r
-#define _CH123SA ADCHSbits.CH123SA\r
-#define _CH123NA ADCHSbits.CH123NA\r
-#define _CH0SB ADCHSbits.CH0SB\r
-#define _CH0NB ADCHSbits.CH0NB\r
-#define _CH123SB ADCHSbits.CH123SB\r
-#define _CH123NB ADCHSbits.CH123NB\r
-\r
-/* ADPCFG */\r
-#define _PCFG0 ADPCFGbits.PCFG0\r
-#define _PCFG1 ADPCFGbits.PCFG1\r
-#define _PCFG2 ADPCFGbits.PCFG2\r
-#define _PCFG3 ADPCFGbits.PCFG3\r
-#define _PCFG4 ADPCFGbits.PCFG4\r
-#define _PCFG5 ADPCFGbits.PCFG5\r
-\r
-/* ADCSSL */\r
-#define _CSSL0 ADCSSLbits.CSSL0\r
-#define _CSSL1 ADCSSLbits.CSSL1\r
-#define _CSSL2 ADCSSLbits.CSSL2\r
-#define _CSSL3 ADCSSLbits.CSSL3\r
-#define _CSSL4 ADCSSLbits.CSSL4\r
-#define _CSSL5 ADCSSLbits.CSSL5\r
-\r
-/* TRISB */\r
-#define _TRISB0 TRISBbits.TRISB0\r
-#define _TRISB1 TRISBbits.TRISB1\r
-#define _TRISB2 TRISBbits.TRISB2\r
-#define _TRISB3 TRISBbits.TRISB3\r
-#define _TRISB4 TRISBbits.TRISB4\r
-#define _TRISB5 TRISBbits.TRISB5\r
-\r
-/* PORTB */\r
-#define _RB0 PORTBbits.RB0\r
-#define _RB1 PORTBbits.RB1\r
-#define _RB2 PORTBbits.RB2\r
-#define _RB3 PORTBbits.RB3\r
-#define _RB4 PORTBbits.RB4\r
-#define _RB5 PORTBbits.RB5\r
-\r
-/* LATB */\r
-#define _LATB0 LATBbits.LATB0\r
-#define _LATB1 LATBbits.LATB1\r
-#define _LATB2 LATBbits.LATB2\r
-#define _LATB3 LATBbits.LATB3\r
-#define _LATB4 LATBbits.LATB4\r
-#define _LATB5 LATBbits.LATB5\r
-\r
-/* TRISC */\r
-#define _TRISC13 TRISCbits.TRISC13\r
-#define _TRISC14 TRISCbits.TRISC14\r
-#define _TRISC15 TRISCbits.TRISC15\r
-\r
-/* PORTC */\r
-#define _RC13 PORTCbits.RC13\r
-#define _RC14 PORTCbits.RC14\r
-#define _RC15 PORTCbits.RC15\r
-\r
-/* LATC */\r
-#define _LATC13 LATCbits.LATC13\r
-#define _LATC14 LATCbits.LATC14\r
-#define _LATC15 LATCbits.LATC15\r
-\r
-/* TRISD */\r
-#define _TRISD0 TRISDbits.TRISD0\r
-#define _TRISD1 TRISDbits.TRISD1\r
-\r
-/* PORTD */\r
-#define _RD0 PORTDbits.RD0\r
-#define _RD1 PORTDbits.RD1\r
-\r
-/* LATD */\r
-#define _LATD0 LATDbits.LATD0\r
-#define _LATD1 LATDbits.LATD1\r
-\r
-/* TRISE */\r
-#define _TRISE0 TRISEbits.TRISE0\r
-#define _TRISE1 TRISEbits.TRISE1\r
-#define _TRISE2 TRISEbits.TRISE2\r
-#define _TRISE3 TRISEbits.TRISE3\r
-#define _TRISE4 TRISEbits.TRISE4\r
-#define _TRISE5 TRISEbits.TRISE5\r
-#define _TRISE8 TRISEbits.TRISE8\r
-\r
-/* PORTE */\r
-#define _RE0 PORTEbits.RE0\r
-#define _RE1 PORTEbits.RE1\r
-#define _RE2 PORTEbits.RE2\r
-#define _RE3 PORTEbits.RE3\r
-#define _RE4 PORTEbits.RE4\r
-#define _RE5 PORTEbits.RE5\r
-#define _RE8 PORTEbits.RE8\r
-\r
-/* LATE */\r
-#define _LATE0 LATEbits.LATE0\r
-#define _LATE1 LATEbits.LATE1\r
-#define _LATE2 LATEbits.LATE2\r
-#define _LATE3 LATEbits.LATE3\r
-#define _LATE4 LATEbits.LATE4\r
-#define _LATE5 LATEbits.LATE5\r
-#define _LATE8 LATEbits.LATE8\r
-\r
-/* TRISF */\r
-#define _TRISF2 TRISFbits.TRISF2\r
-#define _TRISF3 TRISFbits.TRISF3\r
-\r
-/* PORTF */\r
-#define _RF2 PORTFbits.RF2\r
-#define _RF3 PORTFbits.RF3\r
-\r
-/* LATF */\r
-#define _LATF2 LATFbits.LATF2\r
-#define _LATF3 LATFbits.LATF3\r
-\r
-/* RCON */\r
-#define _POR RCONbits.POR\r
-#define _BOR RCONbits.BOR\r
-#define _IDLE RCONbits.IDLE\r
-#define _SLEEP RCONbits.SLEEP\r
-#define _WDTO RCONbits.WDTO\r
-#define _SWDTEN RCONbits.SWDTEN\r
-#define _SWR RCONbits.SWR\r
-#define _EXTR RCONbits.EXTR\r
-#define _BGST RCONbits.BGST\r
-#define _IOPUWR RCONbits.IOPUWR\r
-#define _TRAPR RCONbits.TRAPR\r
-\r
-/* OSCCON */\r
-#define _OSWEN OSCCONbits.OSWEN\r
-#define _LPOSCEN OSCCONbits.LPOSCEN\r
-#define _CF OSCCONbits.CF\r
-#define _LOCK OSCCONbits.LOCK\r
-#define _POST OSCCONbits.POST\r
-#define _NOSC OSCCONbits.NOSC\r
-#define _TUN0 OSCCONbits.TUN0\r
-#define _TUN1 OSCCONbits.TUN1\r
-#define _COSC OSCCONbits.COSC\r
-#define _TUN2 OSCCONbits.TUN2\r
-#define _TUN3 OSCCONbits.TUN3\r
-\r
-/* NVMCON */\r
-#define _PROGOP NVMCONbits.PROGOP\r
-#define _TWRI NVMCONbits.TWRI\r
-#define _WRERR NVMCONbits.WRERR\r
-#define _WREN NVMCONbits.WREN\r
-#define _WR NVMCONbits.WR\r
-\r
-/* PMD1 */\r
-#define _ADCMD PMD1bits.ADCMD\r
-#define _C1MD PMD1bits.C1MD\r
-#define _SPI1MD PMD1bits.SPI1MD\r
-#define _U1MD PMD1bits.U1MD\r
-#define _I2CMD PMD1bits.I2CMD\r
-#define _PWMMD PMD1bits.PWMMD\r
-#define _QEIMD PMD1bits.QEIMD\r
-#define _T1MD PMD1bits.T1MD\r
-#define _T2MD PMD1bits.T2MD\r
-#define _T3MD PMD1bits.T3MD\r
-#define _T4MD PMD1bits.T4MD\r
-#define _T5MD PMD1bits.T5MD\r
-\r
-/* PMD2 */\r
-#define _OC1MD PMD2bits.OC1MD\r
-#define _OC2MD PMD2bits.OC2MD\r
-#define _IC1MD PMD2bits.IC1MD\r
-#define _IC2MD PMD2bits.IC2MD\r
-#define _IC7MD PMD2bits.IC7MD\r
-#define _IC8MD PMD2bits.IC8MD\r
-\r
-\r
-/* -------------------------------------------- */ \r
-/* Macros for Device Configuration Registers */\r
-/* -------------------------------------------- */\r
-\r
-/* FOSC */\r
-#define _FOSC(x) __attribute__((section("__FOSC.sec,code"))) int _FOSC = (x);\r
-\r
-#define CSW_FSCM_OFF 0xFFFF\r
-#define CSW_ON_FSCM_OFF 0x7FFF\r
-#define CSW_FSCM_ON 0x3FFF\r
-#define EC 0xFFFB\r
-#define ECIO 0xFFFC\r
-#define EC_PLL4 0xFFFD\r
-#define EC_PLL8 0xFFFE\r
-#define EC_PLL16 0xFFFF\r
-#define ERC 0xFFF9\r
-#define ERCIO 0xFFF8\r
-#define XT 0xFFF4\r
-#define XT_PLL4 0xFFF5\r
-#define XT_PLL8 0xFFF6\r
-#define XT_PLL16 0xFFF7\r
-#define XTL 0xFFF0\r
-#define FRC_PLL4 0xFFF1\r
-#define FRC_PLL8 0xFFFA\r
-#define FRC_PLL16 0xFFF3\r
-#define HS 0xFFF2\r
-#define LP 0xFCFF\r
-#define FRC 0xFDFF\r
-#define LPRC 0xFEFF\r
-\r
-/* FWDT */\r
-#define _FWDT(x) __attribute__((section("__FWDT.sec,code"))) int _FWDT = (x);\r
-\r
-#define WDT_ON 0xFFFF\r
-#define WDT_OFF 0x7FFF\r
-#define WDTPSA_1 0xFFCF\r
-#define WDTPSA_8 0xFFDF\r
-#define WDTPSA_64 0xFFEF\r
-#define WDTPSA_512 0xFFFF\r
-#define WDTPSB_1 0xFFF0\r
-#define WDTPSB_2 0xFFF1\r
-#define WDTPSB_3 0xFFF2\r
-#define WDTPSB_4 0xFFF3\r
-#define WDTPSB_5 0xFFF4\r
-#define WDTPSB_6 0xFFF5\r
-#define WDTPSB_7 0xFFF6\r
-#define WDTPSB_8 0xFFF7\r
-#define WDTPSB_9 0xFFF8\r
-#define WDTPSB_10 0xFFF9\r
-#define WDTPSB_11 0xFFFA\r
-#define WDTPSB_12 0xFFFB\r
-#define WDTPSB_13 0xFFFC\r
-#define WDTPSB_14 0xFFFD\r
-#define WDTPSB_15 0xFFFE\r
-#define WDTPSB_16 0xFFFF\r
-\r
-/* FBORPOR */\r
-#define _FBORPOR(x) __attribute__((section("__FBORPOR.sec,code"))) int _FBORPOR = (x);\r
-\r
-#define MCLR_EN 0xFFFF\r
-#define MCLR_DIS 0x7FFF\r
-#define RST_IOPIN 0xFFFF\r
-#define RST_PWMPIN 0xFBFF\r
-#define PWMxH_ACT_HI 0xFFFF\r
-#define PWMxH_ACT_LO 0xFDFF\r
-#define PWMxL_ACT_HI 0xFFFF\r
-#define PWMxL_ACT_LO 0xFEFF\r
-#define PBOR_ON 0xFFFF\r
-#define PBOR_OFF 0xFF7F\r
-#define BORV_20 0xFFFF\r
-#define BORV_27 0xFFEF\r
-#define BORV_42 0xFFDF\r
-#define BORV_45 0xFFCF\r
-#define PWRT_OFF 0xFFFC\r
-#define PWRT_4 0xFFFD\r
-#define PWRT_16 0xFFFE\r
-#define PWRT_64 0xFFFF\r
-\r
-/* FGS */\r
-#define _FGS(x) __attribute__((section("__FGS.sec,code"))) int _FGS = (x);\r
-\r
-#define CODE_PROT_OFF 0xFFFF\r
-#define CODE_PROT_ON 0xFFFD\r
-\r
-\r
-/* --------------------------------------------------------------------------- \r
- Setting configuration fuses using macros:\r
- ==========================================\r
- Macros are provided which can be used to set configuration fuses:\r
- For e.g., to set the FOSC fuse using a macro above, the following line of\r
- code can be pasted before the beginning of the C source code.\r
-\r
- _FOSC(CSW_FSCM_ON & EC_PLL16);\r
-\r
- This would enable the external clock with the PLL set to 16x and further,\r
- enable clock switching and failsafe clock monitoring.\r
-\r
- Similarly, to set the FBORPOR fuse, paste the following :\r
-\r
- _FBORPOR(PBOR_ON & BORV_27 & PWRT_ON_64 & MCLR_DIS);\r
-\r
- This would enable Brown-out Reset at 2.7 Volts and initialize the Power-up\r
- timer to 64 milliseconds and configure the use of the MCLR pin for I/O.\r
- Given below, is a complete list of settings valid to each of the fuses:\r
- (Paste the ones relevant to your application before the beginning of C\r
- source code.)\r
-\r
- FOSC:\r
- ======\r
- _FOSC(CSW_FSCM_OFF & EC);\r
- _FOSC(CSW_FSCM_OFF & ECIO);\r
- _FOSC(CSW_FSCM_OFF & EC_PLL4);\r
- _FOSC(CSW_FSCM_OFF & EC_PLL8);\r
- _FOSC(CSW_FSCM_OFF & EC_PLL16);\r
- _FOSC(CSW_FSCM_OFF & ERC);\r
- _FOSC(CSW_FSCM_OFF & ERCIO);\r
- _FOSC(CSW_FSCM_OFF & XT);\r
- _FOSC(CSW_FSCM_OFF & XT_PLL4);\r
- _FOSC(CSW_FSCM_OFF & XT_PLL8);\r
- _FOSC(CSW_FSCM_OFF & XT_PLL16);\r
- _FOSC(CSW_FSCM_OFF & XTL);\r
- _FOSC(CSW_FSCM_OFF & FRC_PLL4);\r
- _FOSC(CSW_FSCM_OFF & FRC_PLL8);\r
- _FOSC(CSW_FSCM_OFF & FRC_PLL16);\r
- _FOSC(CSW_FSCM_OFF & HS);\r
- _FOSC(CSW_FSCM_OFF & LP & EC);\r
- _FOSC(CSW_FSCM_OFF & LP & ECIO);\r
- _FOSC(CSW_FSCM_OFF & LP & EC_PLL4);\r
- _FOSC(CSW_FSCM_OFF & LP & EC_PLL8);\r
- _FOSC(CSW_FSCM_OFF & LP & EC_PLL16);\r
- _FOSC(CSW_FSCM_OFF & LP & ERC);\r
- _FOSC(CSW_FSCM_OFF & LP & ERCIO);\r
- _FOSC(CSW_FSCM_OFF & LP & XT);\r
- _FOSC(CSW_FSCM_OFF & LP & XT_PLL4);\r
- _FOSC(CSW_FSCM_OFF & LP & XT_PLL8);\r
- _FOSC(CSW_FSCM_OFF & LP & XT_PLL16);\r
- _FOSC(CSW_FSCM_OFF & LP & XTL);\r
- _FOSC(CSW_FSCM_OFF & LP & FRC_PLL4);\r
- _FOSC(CSW_FSCM_OFF & LP & FRC_PLL8);\r
- _FOSC(CSW_FSCM_OFF & LP & FRC_PLL16);\r
- _FOSC(CSW_FSCM_OFF & LP & HS);\r
- _FOSC(CSW_FSCM_OFF & FRC & EC);\r
- _FOSC(CSW_FSCM_OFF & FRC & ECIO);\r
- _FOSC(CSW_FSCM_OFF & FRC & EC_PLL4);\r
- _FOSC(CSW_FSCM_OFF & FRC & EC_PLL8);\r
- _FOSC(CSW_FSCM_OFF & FRC & EC_PLL16);\r
- _FOSC(CSW_FSCM_OFF & FRC & ERC);\r
- _FOSC(CSW_FSCM_OFF & FRC & ERCIO);\r
- _FOSC(CSW_FSCM_OFF & FRC & XT);\r
- _FOSC(CSW_FSCM_OFF & FRC & XT_PLL4);\r
- _FOSC(CSW_FSCM_OFF & FRC & XT_PLL8);\r
- _FOSC(CSW_FSCM_OFF & FRC & XT_PLL16);\r
- _FOSC(CSW_FSCM_OFF & FRC & XTL);\r
- _FOSC(CSW_FSCM_OFF & FRC & FRC_PLL4);\r
- _FOSC(CSW_FSCM_OFF & FRC & FRC_PLL8);\r
- _FOSC(CSW_FSCM_OFF & FRC & FRC_PLL16);\r
- _FOSC(CSW_FSCM_OFF & FRC & HS);\r
- _FOSC(CSW_FSCM_OFF & LPRC & EC);\r
- _FOSC(CSW_FSCM_OFF & LPRC & ECIO);\r
- _FOSC(CSW_FSCM_OFF & LPRC & EC_PLL4);\r
- _FOSC(CSW_FSCM_OFF & LPRC & EC_PLL8);\r
- _FOSC(CSW_FSCM_OFF & LPRC & EC_PLL16);\r
- _FOSC(CSW_FSCM_OFF & LPRC & ERC);\r
- _FOSC(CSW_FSCM_OFF & LPRC & ERCIO);\r
- _FOSC(CSW_FSCM_OFF & LPRC & XT);\r
- _FOSC(CSW_FSCM_OFF & LPRC & XT_PLL4);\r
- _FOSC(CSW_FSCM_OFF & LPRC & XT_PLL8);\r
- _FOSC(CSW_FSCM_OFF & LPRC & XT_PLL16);\r
- _FOSC(CSW_FSCM_OFF & LPRC & XTL);\r
- _FOSC(CSW_FSCM_OFF & LPRC & FRC_PLL4);\r
- _FOSC(CSW_FSCM_OFF & LPRC & FRC_PLL8);\r
- _FOSC(CSW_FSCM_OFF & LPRC & FRC_PLL16);\r
- _FOSC(CSW_FSCM_OFF & LPRC & HS);\r
- _FOSC(CSW_ON_FSCM_OFF & EC);\r
- _FOSC(CSW_ON_FSCM_OFF & ECIO);\r
- _FOSC(CSW_ON_FSCM_OFF & EC_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & EC_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & EC_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & ERC);\r
- _FOSC(CSW_ON_FSCM_OFF & ERCIO);\r
- _FOSC(CSW_ON_FSCM_OFF & XT);\r
- _FOSC(CSW_ON_FSCM_OFF & XT_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & XT_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & XT_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & XTL);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & HS);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & EC);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & ECIO);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & EC_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & EC_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & EC_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & ERC);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & ERCIO);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & XT);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & XT_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & XT_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & XT_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & XTL);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & FRC_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & FRC_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & FRC_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & LP & HS);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & EC);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & ECIO);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & EC_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & EC_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & EC_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & ERC);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & ERCIO);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & XT);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & XT_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & XT_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & XT_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & XTL);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & FRC_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & FRC_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & FRC_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & FRC & HS);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & EC);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & ECIO);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & EC_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & EC_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & EC_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & ERC);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & ERCIO);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & XT);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & XT_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & XT_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & XT_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & XTL);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & FRC_PLL4);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & FRC_PLL8);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & FRC_PLL16);\r
- _FOSC(CSW_ON_FSCM_OFF & LPRC & HS);\r
- _FOSC(CSW_FSCM_ON & EC);\r
- _FOSC(CSW_FSCM_ON & ECIO);\r
- _FOSC(CSW_FSCM_ON & EC_PLL4);\r
- _FOSC(CSW_FSCM_ON & EC_PLL8);\r
- _FOSC(CSW_FSCM_ON & EC_PLL16);\r
- _FOSC(CSW_FSCM_ON & ERC);\r
- _FOSC(CSW_FSCM_ON & ERCIO);\r
- _FOSC(CSW_FSCM_ON & XT);\r
- _FOSC(CSW_FSCM_ON & XT_PLL4);\r
- _FOSC(CSW_FSCM_ON & XT_PLL8);\r
- _FOSC(CSW_FSCM_ON & XT_PLL16);\r
- _FOSC(CSW_FSCM_ON & XTL);\r
- _FOSC(CSW_FSCM_ON & FRC_PLL4);\r
- _FOSC(CSW_FSCM_ON & FRC_PLL8);\r
- _FOSC(CSW_FSCM_ON & FRC_PLL16);\r
- _FOSC(CSW_FSCM_ON & HS);\r
- _FOSC(CSW_FSCM_ON & LP & EC);\r
- _FOSC(CSW_FSCM_ON & LP & ECIO);\r
- _FOSC(CSW_FSCM_ON & LP & EC_PLL4);\r
- _FOSC(CSW_FSCM_ON & LP & EC_PLL8);\r
- _FOSC(CSW_FSCM_ON & LP & EC_PLL16);\r
- _FOSC(CSW_FSCM_ON & LP & ERC);\r
- _FOSC(CSW_FSCM_ON & LP & ERCIO);\r
- _FOSC(CSW_FSCM_ON & LP & XT);\r
- _FOSC(CSW_FSCM_ON & LP & XT_PLL4);\r
- _FOSC(CSW_FSCM_ON & LP & XT_PLL8);\r
- _FOSC(CSW_FSCM_ON & LP & XT_PLL16);\r
- _FOSC(CSW_FSCM_ON & LP & XTL);\r
- _FOSC(CSW_FSCM_ON & LP & FRC_PLL4);\r
- _FOSC(CSW_FSCM_ON & LP & FRC_PLL8);\r
- _FOSC(CSW_FSCM_ON & LP & FRC_PLL16);\r
- _FOSC(CSW_FSCM_ON & LP & HS);\r
- _FOSC(CSW_FSCM_ON & FRC & EC);\r
- _FOSC(CSW_FSCM_ON & FRC & ECIO);\r
- _FOSC(CSW_FSCM_ON & FRC & EC_PLL4);\r
- _FOSC(CSW_FSCM_ON & FRC & EC_PLL8);\r
- _FOSC(CSW_FSCM_ON & FRC & EC_PLL16);\r
- _FOSC(CSW_FSCM_ON & FRC & ERC);\r
- _FOSC(CSW_FSCM_ON & FRC & ERCIO);\r
- _FOSC(CSW_FSCM_ON & FRC & XT);\r
- _FOSC(CSW_FSCM_ON & FRC & XT_PLL4);\r
- _FOSC(CSW_FSCM_ON & FRC & XT_PLL8);\r
- _FOSC(CSW_FSCM_ON & FRC & XT_PLL16);\r
- _FOSC(CSW_FSCM_ON & FRC & XTL);\r
- _FOSC(CSW_FSCM_ON & FRC & FRC_PLL4);\r
- _FOSC(CSW_FSCM_ON & FRC & FRC_PLL8);\r
- _FOSC(CSW_FSCM_ON & FRC & FRC_PLL16);\r
- _FOSC(CSW_FSCM_ON & FRC & HS);\r
- _FOSC(CSW_FSCM_ON & LPRC & EC);\r
- _FOSC(CSW_FSCM_ON & LPRC & ECIO);\r
- _FOSC(CSW_FSCM_ON & LPRC & EC_PLL4);\r
- _FOSC(CSW_FSCM_ON & LPRC & EC_PLL8);\r
- _FOSC(CSW_FSCM_ON & LPRC & EC_PLL16);\r
- _FOSC(CSW_FSCM_ON & LPRC & ERC);\r
- _FOSC(CSW_FSCM_ON & LPRC & ERCIO);\r
- _FOSC(CSW_FSCM_ON & LPRC & XT);\r
- _FOSC(CSW_FSCM_ON & LPRC & XT_PLL4);\r
- _FOSC(CSW_FSCM_ON & LPRC & XT_PLL8);\r
- _FOSC(CSW_FSCM_ON & LPRC & XT_PLL16);\r
- _FOSC(CSW_FSCM_ON & LPRC & XTL);\r
- _FOSC(CSW_FSCM_ON & LPRC & FRC_PLL4);\r
- _FOSC(CSW_FSCM_ON & LPRC & FRC_PLL8);\r
- _FOSC(CSW_FSCM_ON & LPRC & FRC_PLL16);\r
- _FOSC(CSW_FSCM_ON & LPRC & HS);\r
- FWDT\r
- =====\r
- _FWDT(WDT_OFF);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_1);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_2);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_3);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_4);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_5);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_6);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_7);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_8);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_9);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_10);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_11);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_12);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_13);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_14);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_15);\r
- _FWDT(WDT_ON & WDTPSA_1 & WDTPSB_16);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_1);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_2);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_3);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_4);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_5);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_6);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_7);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_8);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_9);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_10);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_11);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_12);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_13);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_14);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_15);\r
- _FWDT(WDT_ON & WDTPSA_8 & WDTPSB_16);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_1);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_2);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_3);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_4);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_5);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_6);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_7);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_8);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_9);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_10);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_11);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_12);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_13);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_14);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_15);\r
- _FWDT(WDT_ON & WDTPSA_64 & WDTPSB_16);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_1);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_2);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_3);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_4);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_5);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_6);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_7);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_8);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_9);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_10);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_11);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_12);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_13);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_14);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_15);\r
- _FWDT(WDT_ON & WDTPSA_512 & WDTPSB_16);\r
-\r
- FBORPOR\r
- ========\r
- _FBORPOR(PBOR_OFF & MCLR_DIS);\r
- _FBORPOR(PBOR_OFF & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_20 & PWRT_OFF & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_27 & PWRT_OFF & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_42 & PWRT_OFF & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_45 & PWRT_OFF & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_20 & PWRT_OFF & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_27 & PWRT_OFF & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_42 & PWRT_OFF & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_45 & PWRT_OFF & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_20 & PWRT_4 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_27 & PWRT_4 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_42 & PWRT_4 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_45 & PWRT_4 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_20 & PWRT_4 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_27 & PWRT_4 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_42 & PWRT_4 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_45 & PWRT_4 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_20 & PWRT_16 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_27 & PWRT_16 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_42 & PWRT_16 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_45 & PWRT_16 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_20 & PWRT_16 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_27 & PWRT_16 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_42 & PWRT_16 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_45 & PWRT_16 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_20 & PWRT_64 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_27 & PWRT_64 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_42 & PWRT_64 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_45 & PWRT_64 & MCLR_DIS);\r
- _FBORPOR(PBOR_ON & BORV_20 & PWRT_64 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_27 & PWRT_64 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_42 & PWRT_64 & MCLR_EN);\r
- _FBORPOR(PBOR_ON & BORV_45 & PWRT_64 & MCLR_EN);\r
-\r
- FGS\r
- ====\r
- _FGS(CODE_PROT_OFF);\r
- _FGS(CODE_PROT_ON);\r
-\r
- ---------------------------------------------------------------------------- */\r
-\r
-\r
-/* -------------------------------------------- */ \r
-/* Some useful macros for inline assembly stuff */\r
-/* -------------------------------------------- */\r
-\r
-#define Nop() {__asm__ volatile ("nop");}\r
-#define ClrWdt() {__asm__ volatile ("clrwdt");}\r
-#define Sleep() {__asm__ volatile ("pwrsav #0");}\r
-#define Idle() {__asm__ volatile ("pwrsav #1");}\r
-\r
-/* ---------------------------------------------------------- */ \r
-/* Some useful macros for allocating data memory */\r
-/* ---------------------------------------------------------- */\r
-\r
-/* The following macros require an argument N that specifies */\r
-/* alignment. N must a power of two, minimum value = 2. */\r
-/* For example, to declare an uninitialized array in X memory */\r
-/* that is aligned to a 32 byte address: */\r
-/* */\r
-/* int _XBSS(32) xbuf[16]; */\r
-/* */\r
-/* To declare an initialized array in data EEPROM without */\r
-/* special alignment: */\r
-/* */\r
-/* int _EEDATA(2) table1[] = {0, 1, 1, 2, 3, 5, 8, 13, 21}; */\r
-/* */\r
-#define _XBSS(N) __attribute__((space(xmemory),aligned(N)))\r
-#define _XDATA(N) __attribute__((space(xmemory),aligned(N)))\r
-#define _YBSS(N) __attribute__((space(ymemory),aligned(N)))\r
-#define _YDATA(N) __attribute__((space(ymemory),aligned(N)))\r
-#define _EEDATA(N) __attribute__((space(eedata),aligned(N)))\r
-\r
-/* The following macros do not require an argument. They can */\r
-/* be used to locate a variable in persistent data memory or */\r
-/* in near data memory. For example, to declare two variables */\r
-/* that retain their values across a device reset: */\r
-/* */\r
-/* int _PERSISTENT var1,var2; */\r
-/* */\r
-#define _PERSISTENT __attribute__((persistent))\r
-#define _NEAR __attribute__((near))\r
-\r
-/* ---------------------------------------------------------- */ \r
-/* Some useful macros for declaring functions */\r
-/* ---------------------------------------------------------- */\r
-\r
-/* The following macros can be used to declare interrupt */\r
-/* service routines (ISRs). For example, to declare an ISR */\r
-/* for the timer1 interrupt: */\r
-/* */\r
-/* void _ISR _T1Interrupt(void); */\r
-/* */\r
-/* To declare an ISR for the SPI1 interrupt with fast */\r
-/* context save: */\r
-/* */\r
-/* void _ISRFAST _SPI1Interrupt(void); */\r
-/* */\r
-/* Note: ISRs will be installed into the interrupt vector */\r
-/* tables automatically if the reserved names listed in the */\r
-/* MPLAB C30 Compiler User's Guide (DS51284) are used. */\r
-/* */\r
-#define _ISR __attribute__((interrupt))\r
-#define _ISRFAST __attribute__((interrupt, shadow))\r
-\r
-/* ---------------------------------------------------------- */\r
-/* Some useful macros for changing the CPU IPL */\r
-/* ---------------------------------------------------------- */\r
-\r
-/* The following macros can be used to modify the current CPU */\r
-/* IPL. The definition of the macro may vary from device to */\r
-/* device. */\r
-/* */\r
-/* To safely set the CPU IPL, use SET_CPU_IPL(ipl); the */\r
-/* valid range of ipl is 0-7, it may be any expression. */\r
-/* */\r
-/* SET_CPU_IPL(7); */\r
-/* */\r
-/* To preserve the current IPL and save it use */\r
-/* SET_AND_SAVE_CPU_IPL(save_to, ipl); the valid range of ipl */\r
-/* is 0-7 and may be any expression, save_to should denote */\r
-/* some temporary storage. */\r
-/* */\r
-/* int old_ipl; */\r
-/* */\r
-/* SET_AND_SAVE_CPU_IPL(old_ipl, 7); */\r
-/* */\r
-/* The IPL can be restored with RESTORE_CPU_IPL(saved_to) */\r
-/* */\r
-/* RESTORE_CPU_IPL(old_ipl); */\r
-\r
-#define SET_CPU_IPL(ipl) { \\r
- int DISI_save; \\r
- \\r
- DISI_save = DISICNT; \\r
- asm volatile ("disi #0x3FFF"); \\r
- SRbits.IPL = ipl; \\r
- DISICNT = DISI_save; } (void) 0;\r
-\r
-#define SET_AND_SAVE_CPU_IPL(save_to, ipl) { \\r
- save_to = SRbits.IPL; \\r
- SET_CPU_IPL(ipl); } (void) 0;\r
-\r
-#define RESTORE_CPU_IPL(saved_to) SET_CPU_IPL(saved_to)\r
-\r
-#endif\r
-\r
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) -I. $(CCFLAGS)
braketest:braketest.o
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLDFILE) $(AICLIB)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLD) $(AICLIB)
braketest.hex:braketest
$(CCBIN2HEX) $^
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) -I. $(CCFLAGS)
cantest:cantest.o
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLDFILE) $(AICLIB)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLD) $(AICLIB)
cantest.hex:cantest
$(CCBIN2HEX) $^
dspicaictest:dspicaictest.o
# pic30-elf-gcc $^ -L/usr/pic30-elf/ -Wl --script=$(PWD)/p30f4012.gld -o $@
# pic30-elf-ld -o $@ --script=$(PWD)/p30f4012.gld -L/usr/pic30-elf/ -lpic30-elf -lc-elf $^
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) -Wl $(CCGLDFILE)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) -Wl $(CCGLD)
dspicaictest.hex:dspicaictest
$(CCBIN2HEX) $^
dspictest:dspictest.o
# pic30-elf-gcc $^ -L/usr/pic30-elf/ -Wl --script=$(PWD)/p30f4012.gld -o $@
# pic30-elf-ld -o $@ --script=$(PWD)/p30f4012.gld -L/usr/pic30-elf/ -lpic30-elf -lc-elf $^
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) -Wl $(CCGLDFILE)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) -Wl $(CCGLD)
dspictest.hex:dspictest
$(CCBIN2HEX) $^
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) -I. $(CCFLAGS)
encodertest:encodertest.o
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLDFILE) $(AICLIB)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLD) $(AICLIB)
encodertest.hex:encodertest
$(CCBIN2HEX) $^
$(CCBIN2HEX) $^
freertosAICtest:freertosAICtest.o $(OSOBJS)
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) -Wl $(CCGLDFILE)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) -Wl $(CCGLD)
freertosAICtest.o:freertosAICtest.c
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) $(OSINCDIR) $(CCFLAGS) $(OSFLAGS)
$(CCBIN2HEX) $^
freertostest:freertostest.o $(OSOBJS)
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) -Wl $(CCGLDFILE)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) -Wl $(CCGLD)
freertostest.o:freertostest.c
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) $(OSINCDIR) $(CCFLAGS) $(OSFLAGS)
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) -I. $(CCFLAGS)
motortest:motortest.o
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLDFILE) $(AICLIB)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLD) $(AICLIB)
motortest.hex:motortest
$(CCBIN2HEX) $^
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) -I. $(CCFLAGS)
pwmtest:pwmtest.o
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLDFILE) $(AICLIB)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLD) $(AICLIB)
pwmtest.hex:pwmtest
$(CCBIN2HEX) $^
$(CC) $(CPU) -x c -c $^ $(CCINCDIR) -I. $(CCFLAGS)
serialtest:serialtest.o
- $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLDFILE) $(AICLIB)
+ $(CC) $(CPU) $^ -o $@ $(CCLIBDIR) $(AICLIBDIR) -Wl $(CCGLD) $(AICLIB)
serialtest.hex:serialtest
$(CCBIN2HEX) $^
projects / aic.git / commitdiff