From: Walter Fetter Lages <w.fetter@ieee.org>
Date: Tue, 22 May 2018 17:50:59 +0000 (-0300)
Subject: Fix power lines in aicpower.sch.
X-Git-Tag: v2.1.1^0
X-Git-Url: http://git.ece.ufrgs.br/?a=commitdiff_plain;h=29b52ba1669457df425048aee6d44c2b6c4e4c38;p=aic.git

Fix power lines in aicpower.sch.
---

diff --git a/doc/aic.back.gbr b/doc/aic.back.gbr
new file mode 100644
index 0000000..7a15e7f
--- /dev/null
+++ b/doc/aic.back.gbr
@@ -0,0 +1,1086 @@
+G04 start of page 2 for group 0 idx 0
+G04 Title: (unknown), solder *
+G04 Creator: pcb 20070208 *
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *
+G04 For: santini *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 710000 410000 *
+G04 PCB-Coordinate-Origin: lower left *
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diff --git a/doc/aic.backmask.gbr b/doc/aic.backmask.gbr
new file mode 100644
index 0000000..9a43120
--- /dev/null
+++ b/doc/aic.backmask.gbr
@@ -0,0 +1,352 @@
+G04 start of page 5 for group -4062 idx -4062
+G04 Title: (unknown), soldermask *
+G04 Creator: pcb 20070208 *
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *
+G04 For: santini *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 710000 410000 *
+G04 PCB-Coordinate-Origin: lower left *
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diff --git a/doc/aic.fab.gbr b/doc/aic.fab.gbr
new file mode 100644
index 0000000..059d108
--- /dev/null
+++ b/doc/aic.fab.gbr
@@ -0,0 +1,3301 @@
+G04 start of page 8 for group -3984 idx -3984
+G04 Title: (unknown), fab *
+G04 Creator: pcb 20070208 *
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *
+G04 For: santini *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 710000 410000 *
+G04 PCB-Coordinate-Origin: lower left *
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diff --git a/doc/aic.front.gbr b/doc/aic.front.gbr
new file mode 100644
index 0000000..136f95f
--- /dev/null
+++ b/doc/aic.front.gbr
@@ -0,0 +1,1059 @@
+G04 start of page 3 for group 1 idx 3
+G04 Title: (unknown), component *
+G04 Creator: pcb 20070208 *
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *
+G04 For: santini *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 710000 410000 *
+G04 PCB-Coordinate-Origin: lower left *
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diff --git a/doc/aic.frontmask.gbr b/doc/aic.frontmask.gbr
new file mode 100644
index 0000000..3357f01
--- /dev/null
+++ b/doc/aic.frontmask.gbr
@@ -0,0 +1,352 @@
+G04 start of page 4 for group -4063 idx -4063
+G04 Title: (unknown), componentmask *
+G04 Creator: pcb 20070208 *
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *
+G04 For: santini *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 710000 410000 *
+G04 PCB-Coordinate-Origin: lower left *
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diff --git a/doc/aic.frontsilk.gbr b/doc/aic.frontsilk.gbr
new file mode 100644
index 0000000..99c39ea
--- /dev/null
+++ b/doc/aic.frontsilk.gbr
@@ -0,0 +1,1345 @@
+G04 start of page 7 for group -4079 idx -4079
+G04 Title: (unknown), topsilk *
+G04 Creator: pcb 20070208 *
+G04 CreationDate: Wed Aug 27 18:33:03 2008 UTC *
+G04 For: santini *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 710000 410000 *
+G04 PCB-Coordinate-Origin: lower left *
+%MOIN*%
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diff --git a/doc/aic.pcb b/doc/aic.pcb
index 4d7e448..7bbe80c 100644
--- a/doc/aic.pcb
+++ b/doc/aic.pcb
@@ -1,5 +1,5 @@
 # release: pcb 20070208
-# date:    Tue Aug 26 15:58:42 2008
+# date:    Tue Aug 26 17:05:17 2008
 # user:    santini (Diego Caberlon Santini,,,)
 # host:    eniac.eniac
 
@@ -845,7 +845,7 @@ Via[297500 75000 4000 2000 0 2000 "" ""]
 Via[322500 20000 4000 2000 0 2000 "" ""]
 Via[622500 287500 6000 2000 0 3500 "" ""]
 Via[400000 322500 6000 2000 0 3500 "" ""]
-Via[220000 145000 6000 2000 0 3500 "" ""]
+Via[232500 145000 6000 2000 0 3500 "" ""]
 Via[387500 332500 6000 2000 0 3500 "" ""]
 Via[360000 15000 6000 2000 0 3500 "" ""]
 Via[175000 90000 6000 2000 0 3500 "" ""]
@@ -2115,7 +2115,7 @@ Layer(1 "solder")
 	Line[542500 117500 547500 122500 1000 2000 ""]
 	Line[510000 15000 505000 20000 2500 2000 ""]
 	Line[470000 172500 477500 180000 2500 2000 "clearline"]
-	Line[235000 82500 235000 85000 2500 2000 "clearline"]
+	Line[155000 52500 157500 50000 2500 2000 "clearline"]
 	Line[477500 352500 477500 360000 2500 2000 "clearline"]
 	Line[610000 122500 615000 127500 1000 2000 ""]
 	Line[417500 77500 415000 80000 1000 2000 ""]
@@ -2151,7 +2151,7 @@ Layer(1 "solder")
 	Line[355000 27500 370000 27500 2500 2000 ""]
 	Line[267500 75000 267500 82500 2500 2000 ""]
 	Line[370000 82500 370000 70000 2500 2000 ""]
-	Line[472500 70000 272500 70000 2500 2000 ""]
+	Line[202500 50000 205000 52500 2500 2000 "clearline"]
 	Line[267500 82500 267500 57500 2500 2000 ""]
 	Line[235000 22500 235000 27500 2500 2000 "clearline"]
 	Line[332500 62500 332500 70000 2500 2000 ""]
@@ -2268,9 +2268,9 @@ Layer(1 "solder")
 	Line[175000 22500 177500 20000 2500 2000 "clearline"]
 	Line[177500 20000 232500 20000 2500 2000 "clearline"]
 	Line[232500 20000 235000 22500 2500 2000 "clearline"]
-	Line[275000 70000 217500 70000 2500 2000 "clearline"]
-	Line[217500 70000 215000 72500 2500 2000 "clearline"]
-	Line[215000 72500 215000 82500 2500 2000 "clearline"]
+	Line[205000 52500 205000 57500 2500 2000 "clearline"]
+	Line[472500 70000 267500 70000 2500 2000 "clearline"]
+	Line[157500 50000 202500 50000 2500 2000 "clearline"]
 	Line[200000 87500 200000 85000 2500 2000 "clearline"]
 	Line[200000 85000 202500 82500 2500 2000 "clearline"]
 	Line[202500 82500 215000 82500 2500 2000 "clearline"]
@@ -2358,10 +2358,6 @@ Layer(1 "solder")
 	Line[70300 97500 70000 97200 1000 2000 "clearline"]
 	Line[70000 86300 93800 86300 1000 2000 "clearline"]
 	Line[155000 57500 155000 52500 2500 2000 "clearline"]
-	Line[155000 52500 157500 50000 2500 2000 "clearline"]
-	Line[157500 50000 202500 50000 2500 2000 "clearline"]
-	Line[202500 50000 205000 52500 2500 2000 "clearline"]
-	Line[205000 52500 205000 57500 2500 2000 "clearline"]
 	Text[75000 390000 0 100 "AIC-2.1.0 (c) 2008" "auto"]
 	Text[75000 382500 0 100 "Diego Caberlon Santini" "auto"]
 	Text[75000 375000 0 100 "Walter Fetter Lages" "auto"]
@@ -2445,7 +2441,7 @@ Layer(4 "component")
 	Line[240000 120000 240000 87500 2500 2000 "clearline"]
 	Line[237500 122500 240000 120000 2500 2000 "clearline"]
 	Line[80000 80900 80900 80000 1000 2000 ""]
-	Line[547500 380000 322500 380000 4000 2000 "clearline"]
+	Line[80000 92500 85000 97500 1000 2000 "clearline"]
 	Line[500000 92500 482500 92500 1000 2000 ""]
 	Line[535000 380000 535000 245000 4000 2000 "clearline"]
 	Line[547500 35000 547500 62500 1000 2000 ""]
@@ -2508,8 +2504,8 @@ Layer(4 "component")
 	Line[297500 27500 290000 35000 2500 2000 ""]
 	Line[290000 35000 290000 70000 2500 2000 ""]
 	Line[297500 75000 297500 57500 1000 2000 ""]
-	Line[322500 380000 315000 372500 4000 2000 "clearline"]
-	Line[457500 192500 457500 380000 4000 2000 "clearline"]
+	Line[232500 132500 232500 145000 2500 2000 "clearline"]
+	Line[80000 91800 80000 92500 1000 2000 "clearline"]
 	Line[547500 360000 547500 330000 2500 2000 "clearline"]
 	Line[602500 52500 602500 57500 2500 2000 ""]
 	Line[240000 87500 235000 82500 2500 2000 "clearline"]
@@ -2519,8 +2515,8 @@ Layer(4 "component")
 	Line[415000 22500 415000 82500 1000 2000 "clearline"]
 	Line[602500 340000 625000 317500 2500 2000 "clearline"]
 	Line[512500 37500 512500 27500 2500 2000 ""]
-	Line[200000 90000 215000 105000 2500 2000 "clearline"]
-	Line[215000 105000 215000 112500 2500 2000 "clearline"]
+	Line[87500 102500 87500 155000 1000 2000 "clearline"]
+	Line[85000 100000 87500 102500 1000 2000 "clearline"]
 	Line[625000 97500 632500 97500 1000 2000 ""]
 	Line[435000 90000 442500 97500 1000 2000 "clearline"]
 	Line[622500 100000 625000 97500 1000 2000 ""]
@@ -2549,7 +2545,7 @@ Layer(4 "component")
 	Line[632500 47500 607500 47500 2500 2000 ""]
 	Line[607500 47500 602500 52500 2500 2000 ""]
 	Line[430000 130000 430000 135000 1000 2000 ""]
-	Line[315000 372500 315000 360000 4000 2000 "clearline"]
+	Line[215000 82500 215000 112500 2500 2000 "clearline"]
 	Line[572500 205000 582500 205000 4000 2000 "clearline"]
 	Line[372500 132500 372500 370000 4000 2000 "clearline"]
 	Line[572500 282500 582500 282500 4000 2000 "clearline"]
@@ -2640,7 +2636,7 @@ Layer(4 "component")
 	Line[307500 145000 312500 140000 1000 2000 "clearline"]
 	Line[312500 140000 312500 87500 1000 2000 "clearline"]
 	Line[317500 82500 312500 87500 1000 2000 "clearline"]
-	Line[200000 87500 200000 90000 2500 2000 "clearline"]
+	Line[85000 97500 85000 100000 1000 2000 "clearline"]
 	Line[207500 147500 207500 217500 1000 2000 "clearline"]
 	Line[350000 155000 350000 140000 1000 2000 "clearline"]
 	Line[492500 112500 492500 155000 1000 2000 "clearline"]
@@ -2673,12 +2669,11 @@ Layer(4 "component")
 	Line[92500 102500 90000 100000 1000 2000 "clearline"]
 	Line[90000 100000 90000 90900 1000 2000 "clearline"]
 	Line[90000 90900 80000 80900 1000 2000 "clearline"]
-	Line[80000 91800 80000 92500 1000 2000 "clearline"]
-	Line[80000 92500 85000 97500 1000 2000 "clearline"]
-	Line[85000 97500 85000 100000 1000 2000 "clearline"]
-	Line[85000 100000 87500 102500 1000 2000 "clearline"]
-	Line[87500 102500 87500 155000 1000 2000 "clearline"]
-	Text[75000 370000 0 100 "AIC-2.1.0  (c) 2008" "selected"]
+	Line[547500 380000 462500 380000 4000 2000 "clearline"]
+	Line[462500 380000 457500 375000 4000 2000 "clearline"]
+	Line[457500 375000 457500 190000 4000 2000 "clearline"]
+	Line[547500 360000 547500 380000 4000 2000 "clearline"]
+	Text[75000 370000 0 100 "AIC-2.1.0  (c) 2008" ""]
 	Text[75000 377500 0 100 "Diego Caberlon Santini" ""]
 	Text[75000 385000 0 100 "Walter Fetter Lages" ""]
 )
@@ -2710,8 +2705,6 @@ NetList()
 		Connect("C8-2")
 		Connect("C9-2")
 		Connect("C10-1")
-		Connect("C16-1")
-		Connect("C17-2")
 		Connect("J2-A6")
 		Connect("J2-A28")
 		Connect("J2-B28")
@@ -2730,13 +2723,13 @@ NetList()
 		Connect("U7-13")
 		Connect("U7-20")
 		Connect("U7-28")
-		Connect("U8-1")
-		Connect("U8-8")
 	)
 	Net("+12V" "(unknown)")
 	(
 		Connect("C1-1")
 		Connect("C2-2")
+		Connect("C16-1")
+		Connect("C17-2")
 		Connect("C19-1")
 		Connect("C20-2")
 		Connect("C23-1")
@@ -2747,6 +2740,8 @@ NetList()
 		Connect("J2-B29")
 		Connect("J2-C29")
 		Connect("U1-1")
+		Connect("U8-1")
+		Connect("U8-8")
 		Connect("U9-1")
 		Connect("U9-7")
 		Connect("U9-14")
diff --git a/doc/aic.plated-drill.cnc b/doc/aic.plated-drill.cnc
new file mode 100644
index 0000000..6dee547
--- /dev/null
+++ b/doc/aic.plated-drill.cnc
@@ -0,0 +1,439 @@
+M48
+INCH,TZ
+T18C0.080
+T20C0.120
+T24C0.028
+T25C0.035
+T26C0.042
+T27C0.052
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+%
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diff --git a/doc/aicpower.sch b/doc/aicpower.sch
index 875c78b..57e3cfb 100644
--- a/doc/aicpower.sch
+++ b/doc/aicpower.sch
@@ -448,7 +448,6 @@ T 1100 86500 5 10 1 1 0 0 1
 value=10uFx16V
 }
 C 2000 86000 1 0 0 gnd-1.sym
-C 9400 80100 1 0 0 5V-plus-1.sym
 C 2500 86000 1 0 0 gnd-1.sym
 C 2800 86300 1 90 0 capacitor-1.sym
 {
@@ -745,3 +744,4 @@ N 16000 84600 16400 84600 4
 N 16400 84600 16400 82000 4
 N 2800 82000 16400 82000 4
 N 2800 82000 2800 84000 4
+C 9400 80100 1 0 0 12V-plus-1.sym
diff --git a/doc/attribs b/doc/attribs
new file mode 100644
index 0000000..d0f45b0
--- /dev/null
+++ b/doc/attribs
@@ -0,0 +1,3 @@
+device
+value
+footprint
\ No newline at end of file
diff --git a/doc/gafrc b/doc/gafrc
new file mode 100755
index 0000000..63f854f
--- /dev/null
+++ b/doc/gafrc
@@ -0,0 +1 @@
+(component-library "./sym")
\ No newline at end of file
diff --git a/doc/sym/dsPIC30F4012-P-1.sym b/doc/sym/dsPIC30F4012-P-1.sym
new file mode 100644
index 0000000..d5a751c
--- /dev/null
+++ b/doc/sym/dsPIC30F4012-P-1.sym
@@ -0,0 +1,327 @@
+v 20041228 1
+B 400 0 3600 5600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 300 7600 8 10 0 0 0 0 1
+description=High-Perfomance 16-Bit Digital Signal Controller
+T 3800 5700 5 10 1 1 0 0 1
+refdes=U?
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+numslots=0
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+documentation=http://ww1.microchip.com/downloads/en/DeviceDoc/70135E.pdf
+T 500 5700 9 10 1 1 0 0 1
+device=dsPIC30F4012
+T 300 7000 8 10 0 0 0 0 1
+footprint=DIP28N
+T 300 6800 8 10 0 0 0 0 1
+symversion=0.1
+T 300 6600 8 10 0 0 0 0 1
+author=Walter Fetter Lages <w.fetter@ieee.org> & Diego Caberlon Santini <diegos@ece.ufrgs.br> & Guilherme Strack <guilhermestrack@terra.com.br>
+V 350 5400 52 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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+{
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+pinlabel=OSC1/CLKI
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+pinseq=9
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+pintype=clk
+}
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+{
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+pinlabel=OSC2/RC15
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+pintype=io
+}
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+{
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+}
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+}
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+}
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+}
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\ No newline at end of file
diff --git a/doc/sym/max5062esoic8-1.sym b/doc/sym/max5062esoic8-1.sym
new file mode 100644
index 0000000..5e3d446
--- /dev/null
+++ b/doc/sym/max5062esoic8-1.sym
@@ -0,0 +1,104 @@
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